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  • Blasted away
    . This may produce an hourglass effect, which may help certain applications. An example of an etched glass substrate shows the taper effect of deep etching. This was etched to 1/4-in. depth. Quartz/glass etches quickly and this part was done within 5 min. Texturing roughens surfaces for subsequent
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    technology. Mitsubishi preps electrochemical etching process Mitsubishi Electric Corp. has developed a single-step, hydrofluoric acid electrochemical etching process that can achieve an aspect ratio greater than 60:1 at potentially a tenth of the cost of conventional deep dry etching. Mentor overhauls
  • MICRO: Special Apps
    have finally achieved their long-promised potential as a disruptive technology. A key process used to fabricate many MEMS devices is deep reactive-ion etching (DRIE) of silicon, which enables the creation of vertical trenches or holes that are typically in the 10- to 750- um range. These deep trenches
  • MICRO:Product Technology News (Jan '2000)
    An automated deep-UV spectrophotometer measures samples of thin-film coatings, photoresists, silicon wafers, deep-UV optics, dry fused silica, and calcium fluoride under vacuum or purged conditions. The CAMS-507 DUV provides precise, repeatable reflectance, absorption, and transmission measurements
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    Heard on the Beat (July 13) Commentary & analysis of week's chip news Applied offers deep-trench silicon etch chamber for sub-100-nm DRAM processes SANTA CLARA, Calif.--Applied Materials Inc. today announced a new silicon etch chamber for 200- and 300-mm wafer DRAM fabs needing deep-trench etching
  • MICRO:Building Copperopolis, by Ted Cacouris, p.43 (July '99)
    The semiconductor industry's introduction of copper into the manufacturing process raises some important issues concerning copper contamination. Several key developments have fostered the transition from aluminum to copper interconnects: damascene processing to surmount the difficulties in etching
  • MICRO: Critical Materials?Wafers
    , the wafer is lapped, etched, and polished. Lapping planarizes the wafer and removes most of the deep damage caused by slicing, while etching removes the damage caused by lapping. Lastly, polishing produces the final, top-quality
  • Integrated cooling system lets chips beat the heat
    . In contrast, Georgia Tech's CMOS-compatible technique works at temperatures <260 C and builds microfluidiccooling channels without damaging attached circuits. The scheme works on gigascale integrated (GSI) chips and is fully compatible with conventional flip-chip packaging. Researchers begin by etching

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