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  • Estimating Clock Tree Jitter
    High speed, high-performance timing applications often require a combination of XO/VCXOs, clock generators, clock buffers and jitter cleaning clocks to satisfy system timing requirements. Each component in the clock tree adds phase jitter to the starting reference clock. Care must be taken during
  • A Primer on Jitter, Jitter Measurement and Phase-locked Loops
    As clock speeds and communication channels run at ever higher frequencies, engineers who have previously had little need to consider clock jitter and phase noise are finding that they need to increase their knowledge of these subjects. This primer provides an overview of jitter, offers practical
  • Phase Noise Measurement and Jitter Analysis
    The JS-1000 is a high-performance, characterization/verification solution for testing electrical components or modules in optical transport communication systems with the utmost accuracy and repeatability. The solution is a tailored Phase Noise System that measures clock jitter characteristics
  • Estimating Period Jitter from Phase Noise
    In this application note, the following definitions apply: Cycle-to-cycle jitter-The short-term variation in clock period between adjacent clock cycles. This jitter measure, abbreviated here as JCC, may be specified as either an RMS or peak-to-peak quantity. Jitter-Short-term variations
  • Clock Division with Jitter and Phase Noise Measurements
    As clock speeds and communication channels run at ever higher frequencies, accurate jitter and phase noise measurements become more important, even as they become more difficult and expensive to manage. While measuring ultra low-jitter devices and equipment, the engineer is continually required
  • PLL Jitter and Its Effects in the CAN Protocol
    it possible to generate an internal 40 MHz clock from an external 10 MHz crystal. One drawback in the use of PLL circuits is that they create a small, but still measurable level of transient phase shifts, or jitter. This Technical Brief shows the influence of PLL jitter on Microchip's PIC18 microcontrollers
  • PLL Jitter and its Effects on ECAN TM Technology Communications (.pdf)
    programmable PLLs in their clock generation circuits. One point of interest in the use of PLL circuits is that they create a small, but still measurable, level of transient phase shifts, or jitter. This technical brief shows the influence of PLL jitter on CAN communications using the dsPIC33F/PIC24H
  • Tutorial: When to use a Clock vs. an Oscillator
    Picking the right device for a particular application is dependent on a number of factors, in high performance applications, low jitter and low phase noise are critical given that they have a direct impact on the bit-error rate in high speed serial data transmission applications and the signal

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