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  • Description: TTL I integrated circuits comprise a family of transistor-transistor logic designed for general purpose digital applications. The family has a medium operating speed (20MHz clock rate), good external noise immunity, high fan out, and the capability of driving lines up to 600pF

    • IC Package Type: DIP, Other
    • Logic Family: Transistor-Transistor Logic (TTL)
    • Number of Units in the Chip: 1
    • Operating Temperature: -55 to 125 C

  • Description: TTL I integrated circuits comprise a family of transistor-transistor logic designed for general purpose digital applications. The family has a medium operating speed (20MHz clock rate), good external noise immunity, high fan out, and the capability of driving lines up to 600pF

    • IC Package Type: DIP, Other
    • Logic Family: Transistor-Transistor Logic (TTL)
    • Number of Units in the Chip: 1
    • Operating Temperature: -55 to 125 C

  • Description: TTL I integrated circuits comprise a family of transistor-transistor logic designed for general purpose digital applications. The family has a medium operating speed (20MHz clock rate), good external noise immunity, high fan out, and the capability of driving lines up to 600pF

    • IC Package Type: DIP, Other
    • Logic Family: Transistor-Transistor Logic (TTL)
    • Number of Units in the Chip: 1
    • Operating Temperature: -55 to 125 C

  • Description: The 54S00/74S00 series of product is fabricated with a non-saturating Schottky clamped transistor technique. This family of TTL product consists of very high performance and high power devices.

    • IC Package Type: DIP
    • Logic Family: Transistor-Transistor Logic (TTL)
    • Number of Units in the Chip: 1
    • Operating Temperature: -55 to 125 C

  • Description: Texas Instruments range of Flip-Flops and Latches from the 74LS Family of Low Power Schottky Logic ICs. The 74LS Family use bipolar junction technology coupled with Schottky diode clamps to achieve operating speeds equal to the original 74TTL family but with much lower power

    • IC Package Type: Other
    • Latch Type: S-R, Transparent D
    • Logic Family: Transistor-Transistor Logic (TTL)
    • Pin Count: 16

  • Description: Texas Instruments range of Flip-Flops and Latches from the 74LS Family of Low Power Schottky Logic ICs. The 74LS Family use bipolar junction technology coupled with Schottky diode clamps to achieve operating speeds equal to the original 74TTL family but with much lower power

    • IC Package Type: Other
    • Latch Type: S-R, Transparent D
    • Logic Family: Transistor-Transistor Logic (TTL)
    • Pin Count: 16

  • Description: Texas Instruments range of Flip-Flops and Latches from the 74LS Family of Low Power Schottky Logic ICs. The 74LS Family use bipolar junction technology coupled with Schottky diode clamps to achieve operating speeds equal to the original 74TTL family but with much lower power

    • IC Package Type: PDIP
    • Latch Type: S-R, Transparent D
    • Logic Family: Transistor-Transistor Logic (TTL)
    • Pin Count: 16

  • Description: Texas Instruments range of Flip-Flops and Latches from the 74LS Family of Low Power Schottky Logic ICs. The 74LS Family use bipolar junction technology coupled with Schottky diode clamps to achieve operating speeds equal to the original 74TTL family but with much lower power

    • IC Package Type: PDIP
    • Latch Type: S-R, Transparent D
    • Logic Family: Transistor-Transistor Logic (TTL)
    • Pin Count: 16

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  • Acceleration measurement improvement by application of novel frequency measurement technique for FDS based INS
    The coincidence detector is based on a S - R Flip - Flop build with TTL Logic -Gates, the counters blocks are based on the 4 bit digital counter 74F393, the memory contains the circuits 62256 that are 32,768- word × 8-bit …
  • High Speed Data Link Concepts For Military Aircraft
    A MECL-111 (ECL I C family available from Motorola) flip - flop w a s , accordingly, chosen f o r the 80 MBS demon- s t r a t i o n link, and the required peripheral l o g i c … 80 MHz encoding flip-flop, a new advanced Schottky- TTL family (Fairchild FAST) w a s employed … Most of the pe- ripheral logic requires c a p a b i l i t i …
  • Electronics for engineers and natural scientists
    … 462 Faraday effect 316 color coding 95 fiber-fiber-coupling 316 fiber-optic sensor 316 FAST (Fairchild-Advanced-Schottky TTL ) 446,448,454 code … … 600 field effect transistor, s. FET field emission 145 … … 205 -, triode region 196 -, r -parameters 199 moistening-sensor … … 509 TiefpaB- filtering circuit 360 -, 355 active ribbon cables 502 flagging 479 flank, waste 493 -, rise 493 -, 560 signal flankengetriggertes system 506 Flankenmerker 561 flank steepness of 360, 494 Flash-Converter 389 Flat-pack-Gehause 470 flip - flop , 513 Master-Slave- -,RS …
  • Elements of the applied electronics
    Otherwise, Trigger are the monostable multivibrators as ICs in TTL- and MO technique available generally inverting - and as (see the appendix B15). 15.8 Simple flip - flops with time control The clocked flip-flops called also clocked flip-flops show still a further input, the time input C in contrast with ungetakteten flip-flops additionally to the inputs S and R for the set and reset.
  • `Wireless Bimboards'-the use of programmable gate arrays in a logic design laboratory
    We try to teach good reliable logic design; for example, pure synchronous clocking, with no irregularities like … Reading SSI manuals makes stud- ents think asynchronous S and R are the proper type. Also several forms of enabled D- flip - flops are avail- able as macros. They remove students' tendency to gate the clock, but are almost nonexistent in TTL .
  • Introduction into the electrical measurement
    The image 9.8 shows the principle circuits of a NAND gate in TTL logic and a … Two stable states, bistable flip-flops called the also flip - flops , have and represent simple, digital storages. The asynchronous RS flip-flop The RS flip-flop has a setting input S , a change of the input states is immediately evaluated synchronized not with a time therefore a backspacing input R and outputs Q and the negated output Q. By …
  • A 76 MHz programmable logic sequencer
    Both logic AND and OK arrays are designed for user-programmabilit?, which enables any chosen product term … The critical delay path can be divided into seven major por- tions: input buffer, AND array, AND sense, OR array, OR sense, S - R flip - flop , and output buffer, as shown in Figure 1. The front end of the TTL -compatible input buffer is constructed of CMOS components.
  • Practical electronics
    Relay, 112 reset dominantly 22 RS232, 94, 97 RS flip - flop , 176 resonant frequency, 28 R -L series circuit, 175, 195, 223, 237 feedback, 42, 43 S Order, 63 dead times, 248 transistors 109, 81 separating amplifiers, TTL switching circuits, 219 .
  • Phase Lock Loops and Frequency Synthesis
    … ma , mp , mpo Mp MSB Nnn NAND, NOR, OR NCO NF OP P p(n) P (s ), P n (s ) p (t ) pl , p 2 , . . . PD PLLS Pn Pr Ps PSD Q, QL , QU qRRr R ( s ) R -S Rφ (τ ) R1 … Additional numerators of the simple fraction expansion of R (s )/S (s ) Velocity error constant Inductance, conversion loss, logic state Multiplication factor Exponent, mass of the particle … … plot Numerator of the 1/[1 + G(s )] Flip flop Autocorrelation Resistance Time constant … Tp Tref Ts TTL Txr , Txo v ( t ) , vi ( t ) , v o ( t ) V2 ( s ) v2 ( t …
  • Set theory in the electronics
    A 4 stufiges flip - flop ,,in action are " shown for demonstration sol1 in drawing 8. More and the more detailed information can the digital of modernity logic circuits on a best Ubersichtsartikel of K.-H. Trissl " (physics in our time " 1, 1970, S. 173) or the down angefuhrten Bucher to be removed. [l] find amen valley of of Digital system by B. R. Bannister and D. G. Whitehead 1973, McCraw Hill. The [5] TTL boiling book, Texas Instr.