The Si86xx family is the industry’s highest performing, widest channel count series of unidirectional and bidirectional isolators supporting up to 5 kV and reinforced isolation ratings. Based on Silicon Labs’ patented isolation technology, Si86xx isolators enable robust operation in harsh industrial applications.

Features

• Up to 5000 VRMS isolation
• UL, CSA, VDE certification
• 60-year life at rated working voltage
• High electromagnetic immunity
• Supply voltage 2.5 to 5.5 V
• Independent, bidirectional SDA and SCL isolation channels
• Open drain outputs with 35 mA sink current
• Supports I²C clocks up to 1.7 MH
• Unidirectional isolation channels support additional system signals (Si8605, Si8606)
• –40 to +125 °C temperature range
• Common mode transient immunity 50 kV/μs
• AEC-Q100 qualification
• RoHS-compliant packages
• SOIC-8 narrow body
• SOIC-16 wide body
• SOIC-16 narrow body

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Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

Silicon Labs' family of low jitter non-PLL based fanout buffers produce multiple copies of an input clock at the same frequency with minimal additive jitter. LVDS, LVPECL, HCSL, LVCMOS, SSTL and HSTL buffers are available, including devices that support integrated level translation.

The Si5330 devices are ideal for general purpose clock distribution of differential and single-ended signal formats.

The SL18860 TCXO fanout buffer is used to replicate the RF output of the TCXO used in handheld applications like smart phones, GPS navigation devices and tablet computers. Low power (2.7 mA typ), small size 10-TDFN (1.4 mm x 2.0 mm x 0.75 mm) and very low phase noise (-168 dBc @ 1 MHz) make these devices ideal for handheld applications.

Features:

• Family supports fanout of 2, 4 or 8
• Some devices are spec compatible to Intel’s DB400 and DB800
• Individual OEs for each output
• Output polarity inversion option
• I²C interface available for output control, AC tuning and enable/disable

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Efficient, intelligent and cost-effective balancing of powered device (PD) loads is a critical design consideration for multi-port PoE equipment. Complementing Silicon Labs’ popular Si3452 PSE controllers, Silicon Labs’ PoE power management ICs provide an easy-to-use, energy-efficient and small-footprint solution for streamlining power delivery in managed and unmanaged switches and routers, iPBXs, IP-based security systems, set-top boxes and power injectors.

Silicon Labs’ Si348x power management ICs take advantage of the real-time voltage and current monitoring capabilities of the Si3452 PoE controller to apply active power management based on actual consumption, enhancing the efficient use of switch ports beyond simple classification schemes.

Silicon Labs offers a complete suite of development tools including a graphical user interface (GUI)-based software development tool to enable quick evaluation and design with the Si348x ICs and companion Si3452 devices. The Si3480MS8-KIT development kit implements an 8-port midspan power injector with an intelligent power management LED display, enabling detailed evaluation of the Si3452 in conjunction with the Si3480 8-port power manager. The 24-port SmartPSE24-KIT power management evaluation kit supports SPI or UART-based interfaces and includes comprehensive power management functions to simplify designing with the Si3482 IC.

Silicon Labs' zero delay clock buffer products are used in applications that require zero propagation delay between the input and output clocks. Silicon Labs' zero delay buffers are based on Silicon Labs’ low power, high performance PLL technology and provide low power consumption and allow spread spectrum modulation to propagate through the system for EMI reduction.

Primarily used in high performance systems for clock distribution, these products provide very low skew, jitter and propagation delay, meet very tight setup and hold time requirements, and improve system timing margins. These low delay and skew zero delay buffers offer improved performance, power, and wider frequency range than the competition.

Features:

• PLL-based clock distribution
• Low propagation delay
• Low output-to-output skew
• Low device-to-device skew
• Low output jitter
• Multiple drive strength options
• Wide operation frequency range: 10 to 220MHz
• 3.3V to 2.5V power supply range
• Low power dissipation
• 4, 5, 8 and 9 output devices available
• Programmable skew rise/fall times in output drivers

Silicon Labs' zero delay clock buffer products are used in applications that require zero propagation delay between the input and output clocks. Silicon Labs' zero delay buffers are based on Silicon Labs’ low power, high performance PLL technology and provide low power consumption and allow spread spectrum modulation to propagate through the system for EMI reduction.

Primarily used in high performance systems for clock distribution, these products provide very low skew, jitter and propagation delay, meet very tight setup and hold time requirements, and improve system timing margins. These low delay and skew zero delay buffers offer improved performance, power, and wider frequency range than the competition.

Features:

• PLL-based clock distribution
• Low propagation delay
• Low output-to-output skew
• Low device-to-device skew
• Low output jitter
• Multiple drive strength options
• Wide operation frequency range: 10 to 220MHz
• 3.3V to 2.5V power supply range
• Low power dissipation
• 4, 5, 8 and 9 output devices available
• Programmable skew rise/fall times in output drivers

Silicon Labs' zero delay clock buffer products are used in applications that require zero propagation delay between the input and output clocks. Silicon Labs' zero delay buffers are based on Silicon Labs’ low power, high performance PLL technology and provide low power consumption and allow spread spectrum modulation to propagate through the system for EMI reduction.

Primarily used in high performance systems for clock distribution, these products provide very low skew, jitter and propagation delay, meet very tight setup and hold time requirements, and improve system timing margins. These low delay and skew zero delay buffers offer improved performance, power, and wider frequency range than the competition.

Features:

• PLL-based clock distribution
• Low propagation delay
• Low output-to-output skew
• Low device-to-device skew
• Low output jitter
• Multiple drive strength options
• Wide operation frequency range: 10 to 220MHz
• 3.3V to 2.5V power supply range
• Low power dissipation
• 4, 5, 8 and 9 output devices available
• Programmable skew rise/fall times in output drivers

Silicon Labs' zero delay clock buffer products are used in applications that require zero propagation delay between the input and output clocks. Silicon Labs' zero delay buffers are based on Silicon Labs’ low power, high performance PLL technology and provide low power consumption and allow spread spectrum modulation to propagate through the system for EMI reduction.

Primarily used in high performance systems for clock distribution, these products provide very low skew, jitter and propagation delay, meet very tight setup and hold time requirements, and improve system timing margins. These low delay and skew zero delay buffers offer improved performance, power, and wider frequency range than the competition.

Features:

• PLL-based clock distribution
• Low propagation delay
• Low output-to-output skew
• Low device-to-device skew
• Low output jitter
• Multiple drive strength options
• Wide operation frequency range: 10 to 220MHz
• 3.3V to 2.5V power supply range
• Low power dissipation
• 4, 5, 8 and 9 output devices available
• Programmable skew rise/fall times in output drivers

Silicon Labs' zero delay clock buffer products are used in applications that require zero propagation delay between the input and output clocks. Silicon Labs' zero delay buffers are based on Silicon Labs’ low power, high performance PLL technology and provide low power consumption and allow spread spectrum modulation to propagate through the system for EMI reduction.

Primarily used in high performance systems for clock distribution, these products provide very low skew, jitter and propagation delay, meet very tight setup and hold time requirements, and improve system timing margins. These low delay and skew zero delay buffers offer improved performance, power, and wider frequency range than the competition.

Features:

• PLL-based clock distribution
• Low propagation delay
• Low output-to-output skew
• Low device-to-device skew
• Low output jitter
• Multiple drive strength options
• Wide operation frequency range: 10 to 220MHz
• 3.3V to 2.5V power supply range
• Low power dissipation
• 4, 5, 8 and 9 output devices available
• Programmable skew rise/fall times in output drivers

Silicon Labs' zero delay clock buffer products are used in applications that require zero propagation delay between the input and output clocks. Silicon Labs' zero delay buffers are based on Silicon Labs’ low power, high performance PLL technology and provide low power consumption and allow spread spectrum modulation to propagate through the system for EMI reduction.

Primarily used in high performance systems for clock distribution, these products provide very low skew, jitter and propagation delay, meet very tight setup and hold time requirements, and improve system timing margins. These low delay and skew zero delay buffers offer improved performance, power, and wider frequency range than the competition.

Features:

• PLL-based clock distribution
• Low propagation delay
• Low output-to-output skew
• Low device-to-device skew
• Low output jitter
• Multiple drive strength options
• Wide operation frequency range: 10 to 220MHz
• 3.3V to 2.5V power supply range
• Low power dissipation
• 4, 5, 8 and 9 output devices available
• Programmable skew rise/fall times in output drivers