The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. A HIGH Ecauses both outputs to assume a HIGH state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (V_CC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. A HIGH Ecauses both outputs to assume a HIGH state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (V_CC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. A HIGH Ecauses both outputs to assume a HIGH state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (V_CC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. A HIGH Ecauses both outputs to assume a HIGH state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (V_CC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. A HIGH Ecauses both outputs to assume a HIGH state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (V_CC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74LVC1G19 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. A HIGH Ecauses both outputs to assume a HIGH state.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (V_CC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74LVC1G19-Q100 is a 1-of-2 decoder/demultiplexer with a common output enable. This device buffers the data on input A and passes it to the outputs 1Y (true) and 2Y (complement) when the enable (E) input signal is LOW. A HIGH Ecauses both outputs to assume a HIGH state.

Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 1.65 V to 5.5 V
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• ±24 mA output drive (V_CC = 3.0 V)
• CMOS low power dissipation
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• I_OFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

The HEF4555B contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (nA0 and nA1, an active LOW enable input (nE) and four mutually exclusive outputs which are active HIGH (nY0 to nY3). When used as a decoder, nEwhen HIGH, forces nY0 to nY3 LOW. When used as a demultiplexer, the appropriate output is selected by the information on nA0 and nA1 with nEas data input. All unselected outputs are LOW.

It operates over a recommended V_DD power supply range of 3 V to 15 V referenced to V_SS (usually ground). Unused inputs must be connected to V_DD, V_SS, or another input.

Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C

Applications

• Code conversion
• Address decoding
• Demultiplexing: when using the enable input as data input

CMOS Dual Binary to 1-of-4 Decoder/Demultiplexer with Outputs Low on Select 16-PDIP -55 to 125

The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE= LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LEremains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems.

Features and benefits

• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent controls
• Active HIGH mutually exclusive outputs
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74HC237-Q100 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237-Q100 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE= LOW), the 74HC237-Q100 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LEremains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237-Q100 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent controls
• Active HIGH mutually exclusive outputs
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC.

Features and benefits

• Wide supply voltage range from 2.0 to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Active LOW mutually exclusive outputs
• Input levels:
• For 74HC138: CMOS level
• For 74HCT138: TTL level
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Seven Segment Decoder/Driver, 4000/14000/40000 Series, Configurable Output, CMOS, PDSO16

SN74HC4851 8-Channel Analog Multiplexer/Demultiplexer with Injection-Current Effect Control

The HEF4543B is a BCD to 7-segment latch/decoder/driver for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH blanking input (BL), an active HIGH phase input (PH) and seven buffered segment outputs (Qa to Qg).

The circuit provides the function of a 4-bit storage latch and an 8-4-2-1 BCD to 7-segment decoder/driver. It can invert the logic levels of the output combination. The phase (PH), blanking (BL) and latch enable (LE) inputs are used to reverse the function table phase, blank the display and store a BCD code, respectively.

For liquid crystal displays, a square-wave is applied to PH and the electrical common back-plane of the display. The outputs of the device are directly connected to the segments of the liquid crystal.

It operates over a recommended V_DD power supply range of 3 V to 15 V referenced to V_SS (usually ground). Unused inputs must be connected to V_DD, V_SS, or another input.

Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

The HEF4028B is a 4-bit BCD to 1-of-10 decoder. A 1-2-4-8 BCD code applied to inputs A0 to A3 causes the selected output to be HIGH, the other nine will be LOW. To use as a 1-of-8 decoder with enable, 3-bit octal inputs are applied to inputs A0 , A1 and A2 selecting an output Y0 to Y7 . Input A3 then becomes an active LOW enable, forcing the selected output LOW when A3 is HIGH. The device may also be used as an 8-output (Y0 to Y7) demultiplexer with A0 to A2 as address inputs and A3 as an active LOW data input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V_DD.

Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V
• CMOS low power dissipation
• High noise immunity
• Fully static operation
• 5 V, 10 V, and 15 V parametric ratings
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

BCD TO 7 SEGMENT LATCH/DECODER, SOIC-16; Logic Family / Base Number:MC14511; Logic Type:Latch / Decoder / Driver; No. of Outputs:7Outputs; Logic Case Style:SOIC; No. of Pins:16Pins; Supply Voltage Min:3V; Supply Voltage Max:18V RoHS Compliant: Yes

IC DECODER 1 X 4:10 16SOIC

CMOS BCD-to-Decimal or Binary-to-Octal Decoders/Drivers 16-TSSOP -55 to 125

CMOS BCD-to-Decimal or Binary-to-Octal Decoders/Drivers 16-SOIC -55 to 125

CMOS BCD-to-Decimal or Binary-to-Octal Decoders/Drivers 16-SOIC -55 to 125

CMOS BCD-to-Decimal or Binary-to-Octal Decoders/Drivers 16-SOIC -55 to 125

CMOS BCD-to-Decimal or Binary-to-Octal Decoders/Drivers 16-SO -55 to 125

CMOS 4-Bit Latch/4-to-16 Line Decoder 24-SOIC -55 to 125

CMOS 4-Bit Latch/4-to-16 Line Decoder 24-PDIP -55 to 125

CMOS Dual Binary to 1-of-4 Decoder/Demultiplexer with Outputs High on Select 16-PDIP -55 to 125

CMOS Dual Binary to 1-of-4 Decoder/Demultiplexer with Outputs High on Select 16-SOIC -55 to 125

CMOS Dual Binary to 1-of-4 Decoder/Demultiplexer with Outputs High on Select 16-TSSOP -55 to 125

CMOS Dual Binary to 1-of-4 Decoder/Demultiplexer with Outputs Low on Select 16-SOIC -55 to 125

High Speed CMOS Logic Inverting and Non-Inverting 3-to-8 Line Decoder Demultiplexer 16-CDIP -55 to 125

High Speed CMOS Logic Inverting and Non-Inverting 3-to-8 Line Decoder Demultiplexer 16-CDIP -55 to 125

High Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexers 16-CDIP -55 to 125

Dual 2-to-4 Line Decoder/Demultiplexer 16-SOIC -55 to 125

Dual 2-to-4 Line Decoder/Demultiplexer 16-SOIC -55 to 125

High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-PDIP -55 to 125

High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer with Address Latches 16-SOIC -55 to 125

High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125

1-of-2 Decoder/Demultiplexer 6-SC70 -40 to 85

3-Line to 8-Line Decoders/Demultiplexers 16-SOIC 0 to 70

BCD-To-Decimal Decoders/Drivers 16-PDIP 0 to 70

NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision(TM) Detection 80-HTQFP 0 to 70

NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovision Detection, YPbPR/RBG Inputs 80-HTQFP 0 to 70

Ultralow Power NTSC/PAL/SECAM Video Decoder w/Robust Sync Detector 32-TQFP 0 to 70

10-bit High Quality Single-Chip Digital Video Decoder That Digitizes And Decodes NTSC/PAL/SECAM 80-HTQFP 0 to 70

Video Decoder IC Monitors, TV 80-HTQFP (12x12)

NTSC/PAL/SECAM/Component 10-bit Digital Video Decoder with MacrovisionTM Detection, 3D-YC/5-Line Com 128-HTQFP 0 to 70

10-bit High Quality Single-Chip Digital Video Decoder That Digitizes And Decodes NTSC/PAL/SECAM 80-HTQFP 0 to 70

10-bit High Quality Single-Chip Digital Video Decoder That Digitizes And Decodes NTSC/PAL/SECAM 80-HTQFP 0 to 70

Four-Channel NTSC/PAL Video Decoder With Independent Scalers, Noise Reduction, Auto Contrast, and Fl 128-HTQFP 0 to 70

Four-Channel NTSC/PAL Video Decoder With Independent Scalers, Noise Reduction, Auto Contrast, and Fl 128-HTQFP 0 to 70