MICRO: Wet Surface Technology

John J. Rosato, M. Rao Yalamanchili, Evanson G. Baiya, and Dwight J. Hanson, and Gerhard Eilmsteiner and Andreas Petritsch, Laboratory and production data show that chemical, rinsing, and drying processes can be performed in a single module, enabling fabs to meet the requirements of sub-130-nm technology nodes. ith 130-nm technologies ramping up to full production, the ability to perform a particle-neutral and water spot–free dry during wafer surface preparation has been identified as a technology enabler. Such capability is especially important for devices with high-aspect-ratio attributes such as vias, contacts, deep trenches, and poly-Si features, where water spots form easily at hydrophilic/hydrophobic interfaces. Spots that are large enough to overlap more than one die will result in a definite yield loss, and even smaller water spots can cause killer defects, high leakage currents, critical-dimension variations, and film adhesion problems, all of which also may contribute to yield loss. Identifying the rinse/dry process as a major challenge for sub-130-nm technology nodes, The International Technology Roadmap for Semiconductors (ITRS) set specifications for water spots at less than one per wafer at both the 130- and 100-nm nodes. surface-preparation requirements at those technology levels include particle sizes of 65 and 50 nm, and defect densities of 0.091 and 0.085 per square centimeter, respectively. The ability to achieve those ambitious surface-preparation goals hinges on the ability to combine process steps in order to minimize the number of air-liquid interfaces that the wafer experiences, which will, in turn, reduce the number of surface defects. It will also be important to combine chemical process steps with rinsing and drying operations in a single process vessel, especially in the case of hydrofluoric acid (HF)–last cleaning processes, which are becoming more widespread with the use of sub-30-Å gate oxides. Performing a true HF-last process in a single vessel will