Michael S. Cassady, Ultratech Stepper A case study demonstrates that the use of 1 steppers can result in higher microlithography throughput and MEMS device yields than the use of 1 wafer steppers and scanners have been used for microlithography applications since the early and mid-1980s. However, because of their higher resolution capability and superior stage and alignment performance, 1 steppers have continuously replaced older-generation 1 scanning projection aligners. Cost and yield factors have prompted many fabs to decide in favor of stepper technology. This article, based on a study conduced at a West Coast IC facility with the assistance of Ultratech Stepper (San Jose), compares stepper and scanner performance. The study revealed that the manufacturer could achieve performance, accuracy, productivity, defectivity, yield, andultimatelyreturn-on-investment advantages by converting to 1 stepper technology or even by implementing a mix-and-match strategy. The technology transformation enabled the chipmaker to increase throughput by 12,000 wafer starts in a given time period by lowering mask costs, boosting mask accuracy, improving total overlay, and upping speed binning. Although the semiconductor industry is advancing toward sub-100-nm design rules, many manufacturing facilities fabricate 0.8-µm and larger devices. Facilities producing 2-µm and larger devices have traditionally used 1 projection, proximity printers, or even contact printers. Manufacturers realized early on that contact printing creates large yield losses because that method causes masks to come into direct physical contact with the wafer, allowing residues from the lithography process to be transferred to wafers, generating killer defects. To avoid that problem, the industry introduced proximity and projection aligners. However, proximity aligners require accurate gapping, an added complexity that translates into maintenance and productivity issues. projection scanning systems, and especially wafer step-and-repeat systems, allowed for the complete physical decoupling of the wafer and mask or reticle in the printing process, greatly improving productivity and yield. Interestingly,
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Lithography equipment transfers circuit or device patterns onto a substrate using a patterned mask and a beam of light or electrons to selectively expose a photoresist layer. Overlay metrology systems align the pattern masks or reticules.
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Product Announcements
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The second generation of the SUSS MicroTec MA300 Gen2 is a highly automated mask aligner platform for 300mm and 200mm wafers. It is specifically designed for 3D Packaging, wafer bumping and wafer...
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Dedicated Mask Aligner Solution for High Volume Production of Compound Semiconductors Devices
With the MA100e Gen2 SUSS MicroTec has designed a dedicated mask aligner platform for processing...
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The capabilities of the MA/BA8 Gen3 Mask Aligner can be optionally enhanced with various imprinting techniques for nanotechnology and UV-replication.
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Combining High Resolution with High Throughput and Submicron Precision...
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MPT Coating (Mask Protection Technology) is a release [anti-sticktion] layer between the wafer and mask to minimize resist sticking and reduce mask cleaning. MPT improves yield by reducing defects...
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The MA150e is a low cost solution for R&D and volume production up to 6" substrates. It is widely used in the production of MEMS and telecommunication devices including applications like LEDs,...
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Next Generation Illumination System for SUSS MicroTec Mask Aligners
The MO Exposure Optics provides more light, improved uniformity and customized illumination shaping to further optimize the...
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Precision Wafer Bonding Solution
The SB6/8e is a semi-automatic, computer controlled, stand-alone wafer bonder accommodating 150mm and 200mm wafers respectively. The SB6/8e system features a rigid...
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Topics of Interest
The Titan robotic platform is designed to meet the reliability, repeatability, and durability needs of advanced IC manufacturing in 200- and 300-mm fabs. Features include brushless motors that...
Plasma pre-treatment for low-temperature direct wafer bonding is used worldwide in many different applications. In this process the full wafer surface is exposed to the plasma. Recently, a new process...
Addressing the challenges posed by warp-speed chipmaking advances, the organizers of next month's SPIE microlithography symposium have scheduled several joint sessions covering an array of defect and...
Ingrid B. Peterson, Art D. Klaum, and Ed Hou, RQM aids in the understanding of reticle defect printability and optimizes return on investment by creating a reticle-sampling plan that takes into...
Designed to repair photolithography mask defects at the 65-nm node, the Accura XT+ DualBeam mask-repair system combines a focused ion beam (FIB) column and an environmental scanning electron...