M2077: Programming Guide Integer N PLL Synthesizer 35 - 2500 MHz

M/A-COM's surface mount frequency synthesizers integrate a low noise buffered VCO, phase locked loop circuit and low pass loop filter. The VCO output is coupled into the PLL circuit where the VCO frequency is divided down in a dual modulus prescaler and 18 bit N Counter or feedback divider (7 bit swallow counter and 11 bit programmable divider) to the phase comparison frequency or step size of the PLL. This is usually in the range of 10 kHz to 5 MHz for most applications. The external reference oscillator is also divided down in the 14 bit programmable R Counter or reference divider to the same phase comparison frequency. The divided VCO and divided reference signals are then fed into the phase comparator which produces an error signal whose magnitude is proportional to the phase difference between the two signals. The error signal is then passed through a loop filter to produce the desired performance characteristics and the result is a voltage which is applied to the tuning input of the VCO.