Using a Hardware Module to Interface 8051 MCUs with SPI Serial EEPROMs

AN1197 Using a Hardware Module to Interface 8051 MCUs with SPI Serial EEPROMs The main features of the 25XXX serial EEPROMs are: Author: Alexandru Valeanu * SPI-compatible serial interface bus Microchip Technology Inc. * EEPROM densities from 128 bits to 512 Kbits * Bus speed from 3 MHz to 20 MHz INTRODUCTION * Voltage range from 1.8V to 5.5V * Low power operation The 25XXX series serial EEPROMs from Microchip * Temperature range from -40°C to +125°C Technology support a half-duplex protocol that functions on a master-slave paradigm that is ideally * Over 1,000,000 erase/write cycles suited to data stream applications. The bus is * Built-in write protection controlled by the microcontroller (master), which This application note is part of a series that provide accesses the 25XXX serial EEPROM (slave) via a source code to help users implement the protocol with simple Serial Peripheral Interface (SPI) compatible minimal effort. serial bus. Bus signals required are a clock input (SCK) Figure 1 is the hardware schematic depicting the inter-plus separate data in (SI) and data out (SO) lines. face between the Microchip 25XXX series serialAccess to the 25XXX serial EEPROM is controlled EEPROMs and NXP's P89LPC952 8051-based MCU.CS) input. Maximum clockthrough a Chip Select ( The schematic shows the connections necessaryfrequencies range from 3 MHz to 20 MHz. between the MCU and the serial EEPROM as tested. Communication to the 25XXX serial EEPROM can be The software was written assuming these con- HOLD) if the clock line ispaused via the hold pin ( WP and HOLD pins are tied to VCCnections. The shared with other peripherals on the SPI bus. While the through resistors, because the write-protect and hold EEPROM is paused, transitions on its inputs are features are not used in the examples provided. CS, allowing the MCU toignored, with the exception of service higher priority interrupts. After releasing the HOLD pin, operations resume from the point when the hold was asserted. FIGURE 1: CIRCUIT FOR P89LPC952 MCU AND 25XXX SERIAL EEPROM (1) Vcc 25XX256 P2.1/MOSI 34 P2.3/MISO33 1 8CS VccP89LPC952 P2.4/SS 32 P2.5/SPICLK31 (2) 2 7SO HOLD (2) 3 6 WP SCK