Introduction - The growing demand for AD (automated driving) and ADAS (advanced driver assistance system) features in modern vehicles is driving an increase in the number and complexity of automotive electronic systems. These systems feature numerous sensors that generate a large amount of data and require increased computing power. Coprocessors are often used since a single SoC may not be sufficient to handle the computing requirements. PCI Express® (PCIe) is one of the interfaces commonly used to connect these components. 

Automotive application, such as AD/ADAS, require real-time processing with ultra-low latency. Reliable and robust timing soltions are needed to support the data transfer between processors via PCIe. This paper will discuss the key considerations of PCIe clocking including clock tree architecture, jitter, signalling type, EMI reduction, and stability. 

PCIe in Automotive -  PCI Express is a point-to-point serial interface created in 2003, originally for the computing industry. It is optimized for closed highly integrated systems such as AD/ADAS, domain controllers or zonal controllers found in today’s vehicles. The PCIe standard has become one of the preferred high-speed interfaces for automotive and has a strong, well-established eco-system. PCIe is a bidirectional bus, based on a pair of unidirectional lanes (one in each direction). Up to 16 lanes can be aggregated in parallel to increase transfer rate. The bandwidth of PCIe has doubled with each generation. The transfer rate per lane evolved from 2.5 GT/S (GTransfer/s) with a rate of 250 MB/s per lane in PCIe Gen 1, to 64 GT/s with a rate of 7.56 GB/s in PCIe Gen 6. PCIe Gen 4 is widely used in automotive systems currently. Gen 4 features 16 GT/s, with a rate of 1.97 GB/s per lane. 

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