Time to Rethink Jitter in SerDes Clocks!
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Why It’s Time to Rethink Jitter Analysis of SerDes Reference Clocks in Optical Modules
As optical fiber technology continues to push the limits of data transport speed and efficiency, the challenge falls on silicon SerDes vendors to keep up. One major obstacle? Managing tighter jitter budgets as data rates increase. A challenge in designing faster SerDes chips is meeting increasingly tighter jitter budgets with each new silicon generation. A portion of this jitter budget is allocated to the external reference clock (refclk) that drives the SerDes. Yet, the industry still relies on outdated methods to specify phase jitter in clock and oscillator datasheets.
