Appendix B: Formal Syntax and Semantics

From IEEE Std.1850-2005. Copyright 2005 IEEE. All rights reserved.*

This appendix formally describes the syntax and semantics of the temporal layer.

B.1 Typed-Text Representation of Symbols

Table B.1 shows the mapping of various symbols used in this definition to the corresponding typed-text PSL representation, in the different flavors.

Table B.1: Typed-text symbols in the SystemVerilog, Verilog, VHDL, SystemC and GDL flavors
	System Verilog	Verilog	VHDL	System C	GDL
?	->	->	->	->	->
	=>	=>	=>	=>	=>
?	->	->	->	->	->
?	<->	<->	<->	<->	<->
?	!	!	not	!	!
?	&&	&&	and	&&	&&
?			or
	:	:	to	:	..
? ?	[ ]	[ ]	( )	( )	( )

Note

For reasons of simplicity, the syntax given herein is more flexible than the one defined by the extended BNF (given in Appendix A). That is, some of the expressions which are legal here are not legal under the BNF grammar. Users should use the stricter syntax, as defined by the BNF grammar in Appendix A.

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	System Verilog	Verilog	VHDL	System C	GDL
?	->	->	->	->	->
	=>	=>	=>	=>	=>
?	->	->	->	->	->
?	<->	<->	<->	<->	<->
?	!	!	not	!	!
?	&&	&&	and	&&	&&
?			or
	:	:	to	:	..
? ?	[ ]	[ ]	( )	( )	( )

	System Verilog	Verilog	VHDL	System C	GDL
?	->	->	->	->	->
	=>	=>	=>	=>	=>
?	->	->	->	->	->
?	<->	<->	<->	<->	<->
?	!	!	not	!	!
?	&&	&&	and	&&	&&
?			or
	:	:	to	:	..
? ?	[ ]	[ ]	( )	( )	( )

A Practical Introduction to PSL

TABLE OF CONTENTS

Appendix B: Formal Syntax and Semantics

B.1 Typed-Text Representation of Symbols

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	System Verilog	Verilog	VHDL	System C	GDL
?	->	->	->	->	->
	=>	=>	=>	=>	=>
?	->	->	->	->	->
?	<->	<->	<->	<->	<->
?	!	!	not	!	!
?	&&	&&	and	&&	&&
?			or
	:	:	to	:	..
? ?	[ ]	[ ]	( )	( )	( )