TABLE OF CONTENTS Up until now, we have focused almost exclusively on the temporal layer. In this chapter, we briefly discuss various aspects of the Boolean, modeling and verification layers not yet covered.
The Boolean layer consists of any Boolean expression in the underlying flavor. A Boolean expression is an expression that is evaluated in a single cycle, and has the value true or false. Note that, as in most languages, a Boolean expression may contain a non-Boolean expression. For instance, the Boolean expression a[2:0] > 3'b2 contains the bit vector a[2:0] and the constant 3'b2, both of them non-Boolean.
In addition, any single bit is interpretable as a Boolean expression. For instance, the single bit a[3] may appear anywhere that a Boolean expression is required, even if a[3] may have a non-Boolean value such as X or Z from the four-valued logic of Verilog. In the case that the value is non-Boolean, the bit is interpreted as true or false according to the rules of the underlying flavor, in the same way that the underlying flavor treats such an expression when it appears as the condition of an if-statement.
Finally, in the Verilog, SystemVeriog and SystemC flavors, a bit vector is also interpretable as a Boolean expression, and similarly to a single bit, is interpreted as true or false according to the rules of the underlying flavor, in the same way that the underlying flavor treats such an expression when it appears as...
