The first part of this chapter describes instructions used to access memory in the Itanium architecture. The memory addressing model is much simpler than the one in the Intel x86 architecture. Only one addressing mode is provided, where the address of a load or store operation is contained in a general purpose register. In most cases, the address register can be modified by a fixed quantity after the memory read or write operation is initiated, in preparation for a subsequent memory access. This simple addressing model requires less silicon space to implement, and allows faster memory access. A novel feature in an Intel processor architecture, presented here, is that the placement of data in the memory hierarchy can be influenced by memory allocation hints attached to load or store instructions.

The second part of the chapter describes speculation techniques. Speculation refers to advance execution of instructions, before knowing that their results will actually be needed. The motivation for this is to hide the long latency of some instructions, in particular that of load operations. Two kinds of speculation are possible in the Itanium architecture: control speculation, and data speculation. Both techniques need to be implemented without raising exceptions [2] from speculated instructions. An added benefit is that instruction slots that would have otherwise been left unused could be filled with speculated instructions, which, if speculation is successful, will perform useful work.