Overview

Floating-point exception handling is important for the Itanium architecture. First, compliance with the IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [2] is sought. Second, Itanium and Itanium 2 processors rely on floating-point exceptions to implement completely the floating-point operations defined by the architectural specification.

This chapter examines the way the floating-point exception handling mechanism works in Itanium architecture implementations, with the discussion focused on scalar floating-point instructions.

The IEEE Standard defines five types of floating-point exceptions: invalid operation, division by zero, overflow, underflow, and inexact result exceptions. A trap can be associated with each exception. If an exception whose trap is enabled is signaled, the execution of the program in which the exception occurred is suspended, the trap handler previously specified by the user is activated, and information about the instruction that caused the exception is delivered to it. This terminology is slightly modified in the context of describing floating-point exception behavior on Intel architecture processors. Signaling an exception may also be also referred to as raising an exception. Exceptions that are signaled before a result has been computed are referred to as faults (invalid operation, and division by zero). The denormal operand exception defined in the Intel processor architectures is also a fault. Exceptions that are signaled after a result has been computed are referred to as traps (overflow, underflow, and inexact result). The traps mentioned in the IEEE Standard are referred to as user floating-point exception handlers. In this context, when exceptions are disabled ( masked), then only a status flag has to be set...