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Supplier: Utmel Electronic Limited
Description: Translator LVPECL/LVDS/LVHSTL/SSTL/HCSL to LVCMOS/LVTTL 8-Pin SOIC
- Operating Temperature: -40 to 85 C
- Supply Voltage: 2.5 V
- Output Type: CMOS, ECL, LVDS, LVPECL, PECL, TTL
- Features: Other
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Supplier: Utmel Electronic Limited
Description: Translator CML/LVDS/LVPECL to LVCMOS/LVTTL 8-Pin SOIC N T/R
- Operating Temperature: -40 to 85 C
- Supply Voltage: 3.3 V
- Output Type: CMOS, ECL, LVDS, LVPECL, PECL, TTL
- Features / Standards: Lead Free, RoHS Compliant
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Supplier: Win Source Electronics
Description: LVDS, TTL Output Signal: LVPECL Categories: Integrated Circuits Temperature Range - Operating: -40°C to 85°C (TA) Case / Package: 8-MLF (2x2) Popularity: Medium Fake Threat In the Open Market: 34 pct. Supply and Demand Status: Balance
- Operating Temperature: -40 to 85 C
- Features: Other
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Supplier: Win Source Electronics
Description: HSTL, LVDS, TTL Output Signal: LVPECL Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 85°C (TA) Case / Package: 8-MLF (2x2) Popularity: Medium Fake Threat In the Open Market: 40 pct. Supply and Demand Status: Limited
- Operating Temperature: -40 to 85 C
- Features: Other
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Supplier: Win Source Electronics
Description: Manufacturer: Texas Instruments Win Source Part Number: 1098767-SN65EPT21DR Packaging: Reel - TR Number of Circuits: 1 Mounting: SMD (SMT) Output Type: Non-Inverted Translator Type: Mixed Signal Channel Type: Unidirectional Channels per Circuit: 1 Input Signal: LVDS, PECL Output
- Operating Temperature: -40 to 85 C
- Features: Other
- Package Type: SOIC
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Supplier: Microchip Technology, Inc.
Description: wave, TTL, CMOS, or PECL to LVDS. Please consider this device SY89841U Additional Features Differential LVDS output Single AC coupled input (min. 100mV swing) Input range from DC to 1.0 GHz 2.5V to 3.3V operation Available in 8-Pin SOP or 3x3mm QFN
- Input Voltage: 2.5 to 3.3 volts
- Translation Voltage (Output): 2.5 to 3.3 volts
- Logic Family: LVDS
- Features: Other
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Supplier: ERSAELECTRONICS PTE. LTD.
Description: LVDS/LVPECL to TTL Translator 2-CH 275MHz 1.5ns 8-Pin TSSOP Product overview: MC100EPT26DTG from onsemi is a Logic IC for digital control, signal routing, level logic, timing, buffering, and embedded board design. It is useful for engineers and buyers comparing
- Number of Inputs: 2
- Propagation Delay: 1.5 ns
- Operating Temperature: -40 C
- IC Package Type: Other
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Supplier: ERSAELECTRONICS PTE. LTD.
Description: Translator LVDS/PECL to TTL 1-CH Unidirectional 8-Pin SOIC T/R Product overview: SN65EPT21DR from Texas Instruments is a Logic IC for digital control, signal routing, level logic, timing, buffering, and embedded board design. It is useful for engineers and buyers
- Operating Temperature: -40 C
- Pin Count: 8
- IC Package Type: Other
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Supplier: ERSAELECTRONICS PTE. LTD.
Description: Translator LVDS/PECL to TTL 1-CH Unidirectional 8-Pin VSSOP Tube Product overview: SN65EPT21DGK from Texas Instruments is a Logic IC for digital control, signal routing, level logic, timing, buffering, and embedded board design. It is useful for engineers and buyers
- Operating Temperature: -40 C
- Pin Count: 8
- IC Package Type: Other
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FPGA based extension to the multichannel pixel readout ASIC
The daughter board contains voltage level and LVDS to TTL translators and bias currents control section.
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http://pos.sissa.it/archive/conferences/167/027/Vertex%202012_027.pdf
The testing system for VIPIC (Fig. 3) is based on two PCBs – one used for the IC and decoupling capacitors and second, motherboard, contained logic levels translators and LVDS to TTL converters, bias currents adjustment resistors, daughterboard insertion slot and communication …
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Proceedings of the 2012 International Conference on Communication, Electronics and Automation Engineering
… the receiver hardware design is mostly the same as transmitter, only one difference is that the camera link modulation module parts, using DS90CR287 chip to complete the Camera link data modulation, while achieving TTL level to the Camera link LVDS level translator .
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RX64DTH -a fully integrated 64-channel ASIC for a digital X-ray imaging system with energy window selection
The command decoder block receives commands in LVDS standard [14] from an external controller (typically a PC I/O card buffered with TTL - LVDS translators ) via a serial link, de- codes them, and generates signals to the other blocks on the IC.
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A fast electronic system of the T0 start trigger detector for the ALICE experiment
… RF cables ~30 m long, (FANOUT) four-output analog fanout modules, (LED CAEN 895) fast discriminators, (QTC) charge- to -time converters, (CFD) constant … … digital fanout device, (NIM– LVDS , LVDS–NIM) level translators , (V) analog signals, (NIM, ECL, LV TTL ) standards for transmitted signals …
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CALORIMETRY IN PARTICLE PHYSICS: PROCEEDINGS OF THE ELEVENTH INTERNATIONAL CONFERENCE
… XILINX CPLD, with master clock from the DAQ board, but with possible connection to an internal clock. The signal transmission is in LVDS , through a TTL translator .
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Translators - Clock & Data Distribution
ON Semiconductor offers an extensive portfolio of translators for interfacing different logic levels, including CMOS, TTL , PECL, NECL, CML, HSTL and LVDS . Add to Worksheet .
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CDF Run IIb Silicon Vertex Detector DAQ Upgrade
The electrical protocol of the front and back panels of FTM are LVDS IJPC interface) and TTL IHB interface), respectively. So a CPLD is used as a level translator to enable the FPGAS to drive the data bus directly to the backplane.
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CDF run IIb silicon vertex detector DAQ upgrade
The electrical protocol of the front and back panels of FTM are LVDS (JPC interface) and TTL (FIB interface), respectively. So a CPLD is used as a level translator to enable the FPGAs to drive the data bus directly to the backplane.
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CDF run IIb silicon vertex detector DAQ upgrade
The electrical protocol of the front and back panels of FTM are LVDS (JPC interface) and TTL (FIB inter- face), respectively. So a CPLD is used as a level translator to en- able the FPGAs to drive the data bus directly to the backplane.