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Supplier: Utmel Electronic Limited
Description: Translator LVPECL/LVDS/LVHSTL/S STL/HCSL to LVCMOS/LVTTL 8-Pin SOIC
- Features / Standards: RoHS Compliant
- Operating Temperature: -40 to 85 C
- Output Type: TTL, CMOS, ECL, PECL, LVPECL, LVDS
- Package / Form Factor: Surface Mount Technology (SMT)
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Supplier: Utmel Electronic Limited
Description: Translator CML/LVDS/LVPECL to LVCMOS/LVTTL 8-Pin SOIC N T/R
- Features / Standards: RoHS Compliant, Lead Free
- Operating Temperature: -40 to 85 C
- Output Type: TTL, CMOS, ECL, PECL, LVPECL, LVDS
- Package / Form Factor: Surface Mount Technology (SMT)
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Supplier: RS Components, Ltd.
Description: Differential (ECL) logic level translators that interface with ECL, PECL, CML, LVDS, HSTL, HCSL, TTL, and CMOS devices. Logic Family = LVDS, LVPECL, LVTTL Logic Function = Translator Translation = LVPECL to LVTTL Maximum High Level Output Current = -3mA
- Logic Family: Transistor-Transistor Logic (TTL), LVDS, Other
- Package: TSSOP
- Propagation Delay: 3.25 ns
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Supplier: RS Components, Ltd.
Description: Differential (ECL) logic level translators that interface with ECL, PECL, CML, LVDS, HSTL, HCSL, TTL, and CMOS devices. Logic Family = LVDS, LVPECL, LVTTL Logic Function = Translator Translation = LVPECL to LVTTL Maximum High Level Output Current = -3mA
- Logic Family: Transistor-Transistor Logic (TTL), LVDS, Other
- Package: TSSOP
- Propagation Delay: 3.25 ns
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Supplier: RS Components, Ltd.
Description: LVPECL/LVDS to LVTTL Translator TSSOP8 - Standard Logic - Logic Level Translators
- Logic Family: Transistor-Transistor Logic (TTL), Emitter Coupled Logic (ECL), Other
- Package: TSSOP
- Propagation Delay: 2.2 ns
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Supplier: RS Components, Ltd.
Description: LVPECL/LVDS to LVTTL Translator TSSOP8 - Standard Logic - Logic Level Translators
- Logic Family: Transistor-Transistor Logic (TTL), Emitter Coupled Logic (ECL), Other
- Package: TSSOP
- Propagation Delay: 2.2 ns
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Supplier: Microchip Technology, Inc.
Description: wave, TTL, CMOS, or LVDS to PECL. Please consider this device SY89327L Additional Features Differential PECL output Single AC coupled input (min. 100mV swing) Input range from DC to 1.0 GHz 2.5V to 3.3V operation Available in 3x3mm QFN
- Input Voltage: 2.5 to 3.3 volts
- Logic Family: LVDS, Other
- Translation Voltage (Output): 2.5 to 3.3 volts
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Supplier: Microchip Technology, Inc.
Description: sine wave, TTL, CMOS, or PECL to LVDS. Please consider this device SY89841U Additional Features Differential LVDS output Single AC coupled input (min. 100mV swing) Input range from DC to 1.0 GHz 2.5V to 3.3V operation Available in 8-Pin SOP or 3x3mm QFN
- Input Voltage: 2.5 to 3.3 volts
- Logic Family: LVDS
- Package: SOIC, Other
- Translation Voltage (Output): 2.5 to 3.3 volts
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Supplier: Microchip Technology, Inc.
Description: The SY89321L is a differential LVPECL/CML/LVDSto-LV TTL translator requiring only a single +3.3V power.The SY89321L is functionally equivalent to the SY100EPT21L, but in an ultra-small 8-pin MLF® package that features a 70% smaller footprint. This ultra-small package and low
- Input Voltage: 3.3 volts
- Logic Family: LVDS, Other
- Operating Current: 20 mA
- Package: Other
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Supplier: Microchip Technology, Inc.
Description: , TTL, CMOS, or LVDS to PECL. Please consider this device SY89327L Additional Features Differential PECL output Single AC coupled input (min. 100mV swing) Input range from DC to 1.0 GHz 2.5V to 3.3V operation Available in 8-Pin SOIC, 8 pin TSSOP or 16 pin 3x3mm
- Input Voltage: 2.5 to 3.3 volts
- Logic Family: PECL, LVDS
- Package: SSOP, Other
- Translation Voltage (Output): 2.5 to 3.3 volts
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Supplier: Win Source Electronics
Description: Channels per Circuit: 1 Input Signal: CML, CMOS, HSTL, LVDS, TTL Output Signal: LVPECL Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 85°C (TA) Case / Package: 8-MLF (2x2) Popularity: Medium Fake Threat In the Open Market: 40 pct. Supply
- IC Package Type: Other
- Operating Temperature: -40 to 85 C
- Output Characteristics: Other
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Supplier: Win Source Electronics
Description: : LVDS, PECL Output Signal: TTL Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 85°C (TA) Case / Package: 8-SOIC Alternative Parts (Cross-Reference): 830S21AMILFT; SN65ELT21DR; SN65EPT21DR; SN65ELT21D; Popularity: Medium Fake Threat In the
- IC Package Type: SOIC, Other
- Operating Temperature: -40 to 85 C
- Output Characteristics: Other
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Supplier: Win Source Electronics
Description: Circuit: 1 Input Signal: CML, CMOS, HSTL, LVDS, TTL Output Signal: LVPECL Categories: Integrated Circuits Temperature Range - Operating: -40°C to 85°C (TA) Case / Package: 8-MLF (2x2) Popularity: Medium Fake Threat In the Open Market: 34 pct. Supply and Demand Status: Balance
- IC Package Type: Other
- Operating Temperature: -40 to 85 C
- Output Characteristics: Other
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ADI's AD-SYNCHRONA14-EBZ is an ideal self-contained device to evaluate and prototype applications that need a highly accurate frequency and phase-controlled source clock. It is designed around Analog Devices’ AD9545 and HMC7044 and greatly simplifies clock distribution (read more)
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FPGA based extension to the multichannel pixel readout ASIC
The daughter board contains voltage level and LVDS to TTL translators and bias currents control section.
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http://pos.sissa.it/archive/conferences/167/027/Vertex%202012_027.pdf
The testing system for VIPIC (Fig. 3) is based on two PCBs – one used for the IC and decoupling capacitors and second, motherboard, contained logic levels translators and LVDS to TTL converters, bias currents adjustment resistors, daughterboard insertion slot and communication …
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Proceedings of the 2012 International Conference on Communication, Electronics and Automation Engineering
… the receiver hardware design is mostly the same as transmitter, only one difference is that the camera link modulation module parts, using DS90CR287 chip to complete the Camera link data modulation, while achieving TTL level to the Camera link LVDS level translator .
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RX64DTH -a fully integrated 64-channel ASIC for a digital X-ray imaging system with energy window selection
The command decoder block receives commands in LVDS standard [14] from an external controller (typically a PC I/O card buffered with TTL - LVDS translators ) via a serial link, de- codes them, and generates signals to the other blocks on the IC.
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A fast electronic system of the T0 start trigger detector for the ALICE experiment
… RF cables ~30 m long, (FANOUT) four-output analog fanout modules, (LED CAEN 895) fast discriminators, (QTC) charge- to -time converters, (CFD) constant … … digital fanout device, (NIM– LVDS , LVDS–NIM) level translators , (V) analog signals, (NIM, ECL, LV TTL ) standards for transmitted signals …
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CALORIMETRY IN PARTICLE PHYSICS: PROCEEDINGS OF THE ELEVENTH INTERNATIONAL CONFERENCE
… XILINX CPLD, with master clock from the DAQ board, but with possible connection to an internal clock. The signal transmission is in LVDS , through a TTL translator .
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Translators - Clock & Data Distribution
ON Semiconductor offers an extensive portfolio of translators for interfacing different logic levels, including CMOS, TTL , PECL, NECL, CML, HSTL and LVDS . Add to Worksheet .
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CDF Run IIb Silicon Vertex Detector DAQ Upgrade
The electrical protocol of the front and back panels of FTM are LVDS IJPC interface) and TTL IHB interface), respectively. So a CPLD is used as a level translator to enable the FPGAS to drive the data bus directly to the backplane.
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CDF run IIb silicon vertex detector DAQ upgrade
The electrical protocol of the front and back panels of FTM are LVDS (JPC interface) and TTL (FIB interface), respectively. So a CPLD is used as a level translator to enable the FPGAs to drive the data bus directly to the backplane.
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CDF run IIb silicon vertex detector DAQ upgrade
The electrical protocol of the front and back panels of FTM are LVDS (JPC interface) and TTL (FIB inter- face), respectively. So a CPLD is used as a level translator to en- able the FPGAs to drive the data bus directly to the backplane.