LVDS Programmable Delay Lines

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  • Clock IC provides all critical timing functions on one chip
    The AD9516 series integrates an integer-N synthesizer, two reference inputs, a voltage-controlled oscillator (VCO), programmable dividers, adjustable delay lines and 14 clock drivers, including LVPECL, LVDS and CMOS.
  • Analog Devices Launches 14-Channel Clock Generator With 2.8 GHz VCO
    The AD9516 series integrates an integer-N synthesizer, two reference inputs, a voltage-controlled oscillator (VCO), programmable dividers, adjustable delay lines and 14 clock drivers, including LVPECL, LVDS and CMOS.
  • Analog Devices Launches 14-Channel Clock Generator With 2.8 GHz VCO
    The AD9516 series integrates an integer-N synthesizer, two reference inputs, a voltage-controlled oscillator (VCO), programmable dividers, adjustable delay lines and 14 clock drivers, including LVPECL, LVDS and CMOS.
  • New products
    The AD9516 series integrates an integer-N synthesizer, two reference inputs, a voltage-controlled oscillator (VCO), programmable dividers, adjustable delay lines and 14 clock drivers, including LVPECL, LVDS and CMOS.
  • Development of a high resolution PXI based data acquisition system for electron momentum spectrometer
    The preamplifiers each of which mainly consists of a FA, a non- delay - line CFD are developed and assembled near the detector. The LVDS signals from preamplifiers are fed to the Field- Programmable Gate Arrays (FPGA) from Xilinx Vertex-4 family on time digitizing module for time measurement.
  • The DIALOG chip in the front-end electronics of the LHCb muon detector
    … each one placed on a different chamber layer, for a total of 16 LVDS input physical channels. Each single channel of the 16 DIALOG input channels can be delayed by a 31 programmable steps of ∼ 1.6 ns provided by a VCDL (Voltage Controlled Delay Line ) as explained in section III.
  • Ultra-fast streaming camera platform for scientific applications
    An individual programmable absolute delay primitive block, IODELAY [8], can be used for a precise 80ps step time synchronization between data-to-clock. The LVDS input data line is converted from double-data-rate to two single-ended data lines by a double-data-rate (IDDR) register [8].
  • Laser-Induced Latchup Screening and Mitigation in CMOS Devices
    A National Semiconductor DS90C031 LVDS (low voltage differential signaling) quad differential line driver was thought to have sufficient radiation tolerance to be designed into a recent global positioning system (GPS) upgrade program (the DS90C031 is a fully space qualified manufacturers list (QMLV … … unanticipated latchup susceptibility that rendered the part unacceptable for GPS use, with a delay in the mission …
  • http://www-cs.intel.com/content/dam/doc/datasheet/852gme-chipset-gmch-852pm-chipset-mch-datasheet.pdf
    The panel VDD power, the backlight on/off state and the LVDS clock and data lines are all managed by an internal power sequencer. … requested power-up sequence is only allowed to begin after the power cycle delay time requirement T4 … This is programmed in the Power Cycle Delay bits (Panel Power Cycle Delay and Reference Divider Register …
  • http://qspace.library.queensu.ca/jspui/bitstream/1974/6235/1/Wall_Kieran_A_201012_PhD.pdf
    … – Configurable Logic Block CRC – Cyclic Redundancy Check DDR – Double Data Rate DFM – Design for Manufacture DaS – Delay and Sum EEPROM – Electronically Erasable Programmable Read Only Memory EMC … … – Look Up Table LVDS – Low Voltage Differential … … – Signal Integrety SNR – Signal to Noise Ratio TDL – Tapped Delay Line VGA – Variable …