TABLE OF CONTENTS Sometimes the sampling period of a discrete-time controller is dictated by external factors, such as a preexisting hardware design. When such constraints do not exist, the control system designer must select a suitable sampling period. Some considerations for sampling period selection are listed below.
The shorter the sampling period, the more closely the behavior of the discrete-time system resembles that of the continuous-time system. In the limit as the sampling period approaches zero, the responses of the discrete-time and continuous-time systems become indistinguishable.
If the sampling period is too large, the closed-loop system can experience excessive overshoot, oscillation, or even instability.
The sampling period must result in a Nyquist frequency (half the sampling rate) greater than the highest input signal frequency of interest.
The sampling period must be compatible with the update rate specifications of the I/O devices (such as DACs and ADCs) used in the system design.
The sampling period must be long enough that sufficient time is available for the execution of the controller algorithm and I/O operations during each discrete time step. Additional free time should be available to allow for future enhancements to the controller algorithm.
It is critical that input signal components with frequencies above the Nyquist frequency (which equals half the sampling frequency) have small amplitudes compared with lower frequency components. If an input signal at a frequency above the Nyquist frequency is presented to an ADC, the sampled signal will be aliased to a lower frequency, which can...
