Hardware Verification with SystemVerilog: An Object-Oriented Framework

Part I: SystemVerilog and Verification (The Why and How)

Chapter List

Chapter 2: Why SystemVerilog?
Chapter 3: OOP and SystemVerilog
Chapter 4: A Layered Approach

This part of the handbook explores the use of SystemVerilog for verification and then look at the benefits and drawbacks of using SystemVerilog. In the next chapter we take a brief tour of the features of SystemVerilog.

Next, we weave three different themes together: the evolution of programming in general, the creation of object-oriented programming (OOP) techniques, and the evolution of functional verification. The reason we chose to look at these three themes is to show why OOP exists and how it can be harnessed to benefit verification.

A major theme of this handbook is to build a verification system in layers. OOP techniques are well-suited to this approach. In the last chapter of this section, we'll look at a canonical verification system by using a standard approach to building verification components.

Highlights

If you want to do buzzword-oriented programming, you must use a strongly hyped language.

Mike Johns

We in the functional verification trade, write code for a living. Well, we do that, and also puzzle over code that has been written and that has yet to be written. Because functional verification is a task that only gets more complex as designs become more complex, the language we work in determines how well we can cope with this increasing complexity.

The authors believe that SystemVerilog is an appropriate choice for functional verification, but as with any choice, there are trade-offs. This chapter discusses...

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