This appendix contains a summary of the PIC18Fxx2 architecture, instruction set, and registers. The PIC18Fxx2 family contains the PIC18F242, PIC18F252, PIC18F442, and PIC18F452 members. The PIC18F2x2 architecture has only three parallel ports because of package pin limitations, while the PIC18F4x2 architecture has five parallel ports. Figure A.1 shows a block diagram of the PIC18F2x2 architecture. The machine code and flag settings for each PIC18Fxx2 instruction are given in Figures A.2, A.3, and A.4. An RTL description of each instruction is found in Figures A.5 and A.6. The Special Function Register bit definitions are found in Figures A.7 and A.8. The memory map of the Special Function Registers is shown in Figure A.9. The program memory configuration registers are summarized in Figure A.10, with individual bit definitions found in Figure A.11.

Figure A.1: PIC18F2X2 block diagram. ^[1]

Figure A.2: Byte-oriented, bit-oriented file register operations? ^[2]

Figure A.3: Control operations. ^[3]

Figure A.4: Literal, table read/write operations. ^[4]

Figure A.5: Instruction set RTL description (part 1).

Figure A.6: Instruction set RTL description (part 2).

Figure A.7: Register file summary (part 1). ^[5]

Figure A.8: Register file summary (part 2). ^[6]

Figure A.9: Special function register map. ^[7]

Figure A.10: Configuration register summary. ^[8]

Figure A.11: Configuration register bit definitions.