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Supplier: Lansdale Semiconductor, Inc.
Description: The 5400/7400 series of transistor-transistor logic consists of medium speed TTL integrated circuits. This high noise immunity family was designed for general digital logic applications requiring clock frequencies to 30MHz and switching speeds in the 12-15 ns range under
- Operating Temperature: -55 to 125 C
- Pin Count: 14
- Number of Counters in the Chip: 1
- Package Type: DIP
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Supplier: Lansdale Semiconductor, Inc.
Description: The 5400/7400 series of transistor-transistor logic is a medium-speed, high-noise-immunity family of saturating integrated logic circuits designed for general digital logic applications requiring clock frequencies to 30MHz and switching speeds in the 12-15 ns range under
- Power Dissipation: 160 milliwatts
- Operating Temperature: -55 to 125 C
- Pin Count: 14
- Number of Counters in the Chip: 1
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Supplier: Microchip Technology, Inc.
Description: The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a
- Operating Current: 50 mA
- Clock Frequency: 2,500 MHz
- Supply Voltage: 2.5 V, 3.3 V
- Features: Other
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Supplier: Nexperia B.V.
Description: the nCP0 input and nQ0 becomes the decade output. A HIGH on the nMR input overrides the clocks and sets the four outputs LOW. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current
- Clock Frequency: 55 MHz
- Operating Temperature: -40 to 125 C
- Supply Voltage: 5 V
- Counter Category: Asynchronous (Ripple)
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Supplier: Nexperia B.V.
Description: dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC4040: CMOS level For 74HCT4040: TTL level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2
- Operating Temperature: -40 to 125 C
- Supply Voltage: 5 V
- Counter Category: Asynchronous (Ripple)
- Features: ESD Protection, Other
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Supplier: Nexperia B.V.
Description: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C Applications Control counters Timers Frequency dividers Time-delay circuits
- Operating Temperature: -40 to 125 C
- Supply Voltage: 5 V
- Counter Category: Asynchronous (Ripple)
- Features: ESD Protection, Other
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Supplier: Nexperia B.V.
Description: low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC4020: CMOS level For 74HCT4020: TTL level ESD protection: HBM: ANSI/ESDA/JEDEC JS-001
- Operating Temperature: -40 to 125 C
- Supply Voltage: 5 V
- Counter Category: Asynchronous (Ripple)
- Features: ESD Protection, Other
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Supplier: Transcat, Inc.
Description: transistor-transistor logic (TTL) input and output jacks (1/8" phone) provide power to remote sensors and allow multiple strobes to be daisy-chained to provide wider coverage. The xenon flash tube has a 20 to 50 microsecond flash duration to provide crisp images in brightly lit areas.
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Supplier: ValueTronics International, Inc.
Description: components without removing them from circuits with in-circuit capabilities. Choose the probe that complements your system. Additional Features: Frequency range: DC to 1.5 GHz 1.6 pF Input C 450 Ω Input R Bias/Offset (Tip Nulling) Small size Applications: Digital Design and Debug of
- Bandwidth: 1,500 MHz
- Probe Type: Current, Voltage
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Supplier: ValueTronics International, Inc.
Description: x 340 mm) Weight: 7.3 lbs (3.3 kg) Function/Arbitrary Waveform Generator Waveforms: Sine, Square, Ramp, Pulse, DC, Noise, Cardiac, Gaus Pulse, Exp Rise Arbitrary: 4 Slots for Arbitrary Waveforms Maximum Output Frequency: 25 MHz Sample Rate: 125 MSa/s Frequency Resolution: 1 µHz
- Bandwidth: 100 MHz
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Supplier: ValueTronics International, Inc.
Description: Arbitrary: 4 Slots for Arbitrary Waveforms Maximum Output Frequency: 25 MHz Sample Rate: 125 MSa/s Frequency Resolution: 1 μHz Frequency Accuracy: ±50 ppm Vertical Resolution: 14 bits Amplitude Range: -1.5 to +1.5 V @ 50 Ω; -3 to +3 V @ 1 MΩ Output Impedance: 50 Ω ±2%
- Bandwidth: 200 MHz
- Number of Input Channels: 4 (# channels)
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. The high-performance PLL has a -239 dBc/Hz for normalized in-band phase noise floor, ultra-low 1/f noise, and a high phase/frequency detector (PFD) frequency that can achieve ultra-low in-band noise and integrated jitter. The fundamental VCO and output divider of the ADF4378 generate frequencies (read more)
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Photon Counting Optical Time Domain Reflectometry Applying a Single Photon Modulation Technique
A transistor- transistor logic ( TTL ) signal from a frequency di- vider (1/10) was added onto the digital port of AOM’s driver.
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Jitter and phase noise in frequency dividers
, of the output frequency for the transistor-transistor logic ( TTL ) family dividers to be approximately .
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A radiotherapy dose integrator for 300 kVp x-rays.
This frequency is reduced by digital transistor-transistor logic ( TTL ) divider circuitry so that one rad of dose yields one pulse.
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A radiotherapy dose integrator for 300 kVp X-rays
This frequency is reduced by digitaltransistor-transistor . logic ( TTL ) divider circuitry so that one rad of dose yields one pulse.
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Standard Handbook of Broadcast Engineering > AM and FM Receivers
Frequency dividers are commonly built using transistor-transistor logic ( TTL ), complementary MOS (CMOS), and low-power emitter-coupled logic (ECL) IC technologies.
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Phase noise performance of analog frequency dividers
Abstract-The phase noise performance obtainable using TTL and ECL logic level, silicon and GaAs-based, digital frequency dividers is available in the literature.
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Phase noise performance of analog frequency dividers.
The phase noise performance obtainable using silicon and GaAs-based TTL (transistor-transistor logic ) and ECL (emitter-coupled logic) logic level digital frequency dividers is discussed.
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A Precision Pressure Tranducer with FM Output in UHF Band
The use of these dividers (or prescalers) allows one to reduce the frequency to the range where low cost,low power,CMOS or TTL logic circuitry can be usedto perform counting and micro-processor interfacing.
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The pursuit for low cost and low phase noise synthesized signal sources: Theory & optimization
Such a divider is built with logic gates, using typical technologies as TTL , CMOS/BiCMOS, and ECL, but rarely as a regenerative divider based on frequency mixers.
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CR4 - Thread: Signal Processing
… and 24 volt over the 4KΩ). regarding with time of te pulse 2ms is means 1/2ms *1000 Hz =500Hz and 10ms=100Hz so you can use divider frequency logic I.C to divide … … for this process use TTL LOGIC I.C SN7490 …