TABLE OF CONTENTS Walt Jung, Walt Kester
In the early days of high speed circuits, simple emitter followers were often used as high speed buffers. The term buffer was generally accepted to mean a unity-gain, open-loop amplifier. With the availability of matching PNP transistors, a simple emitter follower can be improved, as shown in Figure 6-66A. This complementary circuit offers first-order cancellation of dc offset voltage, and can achieve bandwidths greater than 100 MHz. Typical offset voltages without trimming are usually less than 50 mV, even with unmatched discrete transistors. The HOS-100 hybrid amplifier from Analog Devices represented an early implementation of this circuit. This device was a popular building block in early high speed ADCs, DACs, sample-and-holds, and multiplexers.
If high input impedance is required, a dual FET can be used as an input stage ahead of a complementary emitter follower, as shown in Figure 6-66B. This form of the buffer circuit was implemented by both National Semiconductor Corporation as the LH0033, and by Analog Devices as the ADLH0033.
In the realizations of these hybrid devices, thick film resistors were laser trimmed to minimize input offset voltage. For example, in the Figure 6-66(B) circuit, R1 is first trimmed to set the bias current in the dual matched FET pair, which is from the 2N5911 series of parts. R2 is then trimmed to minimize the buffer input-to-output offset...
