TABLE OF CONTENTS Increasingly, the performance of a modern computer system is determined by the performance of its memory hierarchy. While on-chip operation speeds have been dramatically improving, the performance of memory has mostly remained constant. As a result, the latencies to main memory in terms of processor cycles have been increasing. These latencies must be ameliorated if the machine performance is to keep pace with the performance of the processor.
In this chapter, we will discuss the first of several ways to improve performance of the memory hierarchy through compiler transformations. Every computer system currently in use has some kind of processor register set. Registers are particularly important on RISC architectures, where all operations except loads and stores require that the operands be taken from processor registers and all results be assigned to registers.
Most modern machines also feature some sort of cache memory; however, some do not. Examples of machines without cache include vector processors and the Tera MTA series, in which each thread has its own register set. We will postpone the discussion of compiler management of cache until Chapter 9.
