13.1 Introduction

An exception is an asynchronous event or error condition that disrupts the normal flow of thread processing. Usually, an exception must be handled immediately, and then control is returned to thread processing. There are three exception categories in the ARM architecture, as follows:

• Exceptions resulting from the direct effect of executing an instruction

• Exceptions resulting as a side effect of executing an instruction

• Exceptions resulting from external interrupts, unrelated to instruction execution

When an exception arises, ARM attempts to complete the current instruction, temporarily halts instruction processing, handles the exception, and then continues to process instructions.

The processor handles an exception by performing the following sequence of actions.

1. Save the current value of CPSR into the SPSR of the new operating mode for later return.

2. Change to the operating mode corresponding to the exception.

3. Modify the CPSR of the new operating mode. Clear the T (Thumb) bit (bit 5) in preparation for execution in ARM 32-bit mode. If an IRQ interrupt is present, set the I-bit (bit 7) to disable further IRQ interrupts. If an FIQ interrupt is present, set the F-bit (bit 6) and the I-bit (bit 7) to disable further FIQ interrupts.

4. Save the current PC (program counter address of the next instruction) in register r14 of the new operating mode.

5. Change the PC to the appropriate exception vector as illustrated in Figure 13.1, which is where the application software interrupt handling starts.

ARM has a simple exception and interrupt handling architecture. There are seven interrupt vectors,...