TABLE OF CONTENTS Digital filtering designs may require different implementation approaches dependent on the application speed and power dissipation. Many of them can be easily and effectively implemented using standard floating-point DSP processors. Unfortunately these requiring fast operation speeds and lowpower dissipation require design specific structural implementation. One of the most important ways of achieving high operation speeds is by using constrained coefficients filters with calculations performed in fixed-point arithmetic. This drastically simplifies implementation of Arithmetic-Logic Units (ALU) which in consequence increases the speed of their operation.
The use of constrained filter coefficients is not easy from the point of view of the designer. Constraining coefficients to the certain bit-wordlength makes it impossible to achieve optimal filter performance as in most of the cases the best filter (floating-point) can not be represented with a small number of bits. It happens very often that for LBit-long wordlength the optimum filter is not the one, which has its coefficient values closest to their floating-point versions (best one). Therefore rounding up or down and truncating floating-point coefficients does not give the best result. Some different design approaches have to be used. Unfortunately there is a lack of good coefficient constrained algorithms. The ones found in literature [23], [61] were not described in a way that allowed their easy implementation and performance comparison with other ones.
Constrained filter design methods can be put into two groups. Some methods first calculate the best floating-point filter coefficients, truncate or round them and optimise the...
