Chapters 3 and 4 presented an overview of IEEE 1588 components and systems, and a detailed analysis of the protocol. This chapter discusses a number of practical issues that must be considered in implementing IEEE 1588.
Since the standard was published in the fall of 2002, there have been many independent implementations of IEEE 1588 end devices and boundary clocks. Several of these are described in the proceedings of the IEEE 1588 conferences [27] [28] [29]. From these presentations and the ensuing discussions at the conferences, a number of design patterns and critical design issues have emerged. These issues fall into the following categories, each of which will be discussed in detail in the following sections:
Clock and boundary clock design,
Clock servo design,
Oscillator selection and environment issues,
Issues with non-Ethernet protocols, and
Synchronizing to UTC sources
A general architecture for an IEEE 1588 clock was presented in Figure 3.11 of Section 3.3.4. All of the implementations to date follow this general design. This section deals with practical issues in implementing this or similar architectures.
The discussion will be based on Figure 5.1, which illustrates the general clock architecture in more detail. The figure assumes an Ethernet implementation where the media-independent interface (MII) is the link between the PHY and the rest of the protocol stack. However, the general architecture applies to most networks. Note that many of the blocks shown in this figure will be present in any microprocessor-based node, even...
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