TABLE OF CONTENTS The growing number of users and the demand for high-speed wireless communications has motivated designers to move from the 1 2 GHz range towards higher frequency bands. Recently, new standards in the 5 GHz range for wireless local area network (WLAN) applications have been defined, such as the IEEE 802.11a standard for the FCC unlicensed national information infrastructure (U-NII) band in the US, and the high performance radio LAN (HIPERLAN) standard in Europe.
Traditionally, radio frequency integrated circuits (RFICs) were implemented in GaAs or SiGe bipolar technologies, because of their relatively high unity gain cutoff frequencies f T (i.e. >65 GHz) and their superior noise performance. However, as the minimum feature size of CMOS devices decreases, the f T of the transistors continues to improve to the point where it is becoming comparable to those of GaAs and SiGe processes. Deep-submicron CMOS devices with f T's exceeding 100 GHz and minimum noise figures (NF) less that 0.5 dB at 2 GHz have been demonstrated [1]. Because of these promising RF performances, together with the advantages of low cost and ease of integration with baseband digital circuitry, CMOS is becoming a viable alternative for RF applications, with continuous efforts towards implementing higher frequency circuitry operating from lower supply voltages (e.g. [2-15]).
This chapter starts by introducing a CMOS low noise amplifier (LNA) architecture suitable for operation from sub-1 V supplies. Experimental results from several fabricated prototype chips are presented to demonstrate...
