TABLE OF CONTENTS The continuing reduction in production costs and improvements in personal communication systems has led to a tremendous growth in the wireless communications market. For cheap wireless terminals, it is attractive to integrate the RF frontend with the backend signal processing to reduce assembly cost. Until now, power amplifiers for wireless applications were produced almost exclusively in GaAs technologies, with a few exceptions in LDMOS, Si BJT and SiGe HBT. While CMOS provides high functionality and complexity at low costs, for an RF power amplifier, the problem of using CMOS technology is more severe than other blocks in the transceiver due to the limited voltage-handling capability. The linearity and power efficiency are lower than other technologies. Therefore, implementation of RF power amplifiers in CMOS has been one of the most challenging tasks for wireless transmitters. The design of power amplifiers in CMOS technology is mainly affected by the following factors.
Low breakdown voltage of deep-submicron technologies. This limits the maximum gate drain voltage since the output voltage at the transistor's drain normally reaches 2 times the supply for classes B and F, and around 3 times the supply for class E operation. Thus, transistors have to operate at a lower supply voltage, delivering lower power. Additionally CMOS technology has lower current drive; i.e. the gain provided by the single stage is very low. Either multiple stages would be used or new design techniques, which would reduce the number of stages by decreasing the...
