TABLE OF CONTENTS The turbodecoding algorithm of product codes (iterative decoding algorithm with soft input and output of product codes) described previously offers remarkable performances in terms of correction of transmission errors (residual bit error rates (BER) for a given level of noise). Its complexity of integration onto microchips and DSP is the subject of this chapter.
The impact of integration constraints and the quantification of data on theoretical performances obtained previously are evaluated first. The number of quantification bits directly conditions the complexity of the circuit, in particular with respect to the size of the memories. Two types of architecture are then presented before proposing a decomposition of the elementary decoder into blocks and evaluating its complexity.
In a digital circuit, data is represented by discrete values coded with a finite number q of binary characters. The higher this number is, the more precise the data representation is and the better its performances are. On the other hand, the complexity of the circuit increases with the value of the parameter q (size of the memories and the processing unit). It should be optimized in order to obtain the best performances/complexity compromise.
Using simulation we may study the evolution of the BER for the product code BCH(64,57,4) ?BCH(64,57,4) according to the signal-to-noise ratio E b/N 0. For four decoding iterations the degradation of the...
