TABLE OF CONTENTS The previous chapters have focused primarily on the transition from a single-threaded desktop programming model to one that uses multiple threads on multiple processors. As noted along the way, HT Technology occasionally adds an extra dimension to parallel programming considerations. This chapter examines these aspects in further detail.
To discuss these issues and present cogent explanations for our recommendations, we have to descend fairly deeply into the processor silicon. While programmers typically enjoy knowing more about the hardware their routines are exploiting, some of you might not need or care about this level of detail. If you want the recommendations without the supporting detail, we recommend going to the last section of this chapter, entitled "Key Points." In previous chapters, this section has been a set of bullet points that recaps the previous information. However, in this chapter, we have expanded these points to enable this section to serve as an abridgement of the hands-on recommendations, rather than a simple recapitulation.
All processors today use execution pipelines consisting of multiple stages in which instructions are fetched, analyzed, manipulated, executed, and retired. The idea behind the pipeline design is to handle the execution of instructions in simultaneous, incremental steps. The Intel 8086 processor had two stages: fetch and execute. While the processor was executing an instruction, it was simultaneously fetching the next instruction. With each tick of the processor clock, the chip would move the newly fetched instruction into the execution stage, and while it...
