Memory Systems: Cache, DRAM, Disk
By Samuel Rodriguez

Index

1-bit memory cell, 259-62
cross-coupled inverters, 259
physical implementation, 259-60
soft error rate, 262
static noise margin (SNM), 260-61
transistor sizing, 260-62
2T command timing, 454
2.5-V Series Stub Terminated Logic (SSTL-2), 473-74
3DWinbench, 548-50
6-transistor memory cell (6TMC), 856
164.gzip, 544-45
close-page systems, 565-66
defined, 544
maximum sustainable bandwidth, 563, 565
open-page systems, 561-62
SETI@HOME, 566-67
summary, 543
trace overview, 544
172.mgrid, 547
176.gcc, 545
178.galgel, 548-50
179.art, 548-50
defined, 550
scheduling policy impact, 589
183.equake, 548-50
188.ammp, 548-50
defined, 550
scheduling policy impact, 590
197.parser, 545-46
255.vortex, 546-47
defined, 546-47
maximum sustainable bandwidth, 563
open-page systems, 562
overview, 547
summary, 543
SETI@HOME, 547-48.

A

access protocol
DDR SDRAM, 472
Direct RDRAM, 483-85
DRAM, 427-28
FB-DIMM, 526-30
SDRAM, 469
access time, estimating, 718-19
actuators, 634-35
dual, 711-12
dual stage, 792-94
linear, 634
microactuators, 793-94
rotary, 634-35
top views, 634
VCM, 646
adaptive formatting, 794-96
defined, 795
Deskstar 7K500, 808
effects, 796
address aliasing, 510-11
address decoding, 262-68
concept, 262
concern, 262-63
decode hierarchy, 263
divided wordline (DWL), 265-66
hierarchical word decoding (HWD), 266-67
nonpartitioned, 265
predecoding, 263-64
pulsed wordline, 267-68
row and column, 264-65
two-dimensional, 265
See also decoder implementation
addresses
AMB, 530
distribution, 575
read transaction percentage, 575
shadow, 502
address mapping, 497, 502-11
baseline, 505-6
configuration registers, 507-8
defined, 498
disk drive, 654-57
external, 654
in Intel 82955X MCH, 506-10
internal, 654
logical address to physical location, 655-57
parallelism, 503-4
parameter, 504-5
per-rank schemes, 508-9
virtual memory, 886-87
address spaces
identification, 96
identifier, 886
multiple processes,...
Copyright Elsevier Inc. 2008 under license agreement with Books24x7
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