The Virtual Interface Architecture
Providing guidance for both developers and users of large clustered systems, this book explains how VI provides a new interface between applications and switched interconnect hardware.
TABLE OF CONTENTS The Virtual Interface Architecture
Chapter 5: Memory Translation and Protection
This chapter describes the VI Architecture memory translation and protection scheme. A reference design for a Translation and Protection Table is described. This knowledge will provide the reader with the information needed to use and understand the VI Architecture memory protection and translation mechanism. It will also help hardware designers who are implementing VI NICs.
Overview
The VI Architecture allows applications to use virtual addresses when initializing the descriptor data structures that are executed by the VI NIC. Since the application talks directly to the hardware, bypassing the operating system, the NIC hardware must be able to translate these addresses into physical addresses that are used for memory bus transactions.
In addition to translating virtual addresses into physical addresses, the NIC must enforce memory protection among applications and between applications and the operating system. An application must not be able to cause data to be read from, or written to, memory locations outside of its address space.
The mechanism used by a VI NIC for translation and protection is called (not surprisingly) the Translation and Protection Table (TPT). The implementation of the TPT is outside the scope of the VI Architecture, but the VI Architecture Specification does contain a reference hardware implementation, which is described in this chapter.
TPT Format
The format of the reference TPT is shown in Figure 5.1. A TPT entry consists of three fields:
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A physical page address
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Protection attributes, and
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A protection tag
Figure 5.1: Translation and Protection Table Format
The physical page address field...
Copyright Intel Corporation 2002 under license agreement with Books24x7
