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  • IC Mask Design: Essential Layout Techniques
    IC Mask Design: Essential Layout Techniques. Now you don't need an engineering background to master basic integrated circuit mask design! In this straightforward, jargon-free tutorial, you'll find everything you need to understand every phase and practical technique of IC mask design.
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    was flat and IC layout was soaring. Far from being the death of pc-board design, system-on-chip (SoC) silicon will probably
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    Synopsys executive predicts end of VHDL Synopsys' chairman and chief executive officer Aart de Geus predicted that VHDL will go away in 10 years. De Geus made his prediction at the Synopsys Developers Forum here. BindKey overhauls rules-driven layout tool Promising to bring relief to full-custom IC
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    Innoveda snags PADS in pc-board play In a bid to become a powerhouse in pc-board design, Innoveda Inc. has agreed to acquire PADS Software Inc. The purchase, valued at $32 million, will marry Innoveda's design-entry and analysis tools with PADS' board layout, IC packaging, and signal-integrity
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    sails, with executives stating that it remains business as usual for the company's most advanced plant. Layout tool speeds MEMS design GenISys has started sampling to designers of MEMS based devices, sensors and flat panel displays a flexible simulation platform for mask aligner lithography that lets
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    . The purchase, valued at $32 million, will marry Innoveda's design-entry and analysis tools with PADS' board layout, IC packaging, and signal-integrity software. U.S. official raps German role in lithography group The U.S. Commerce Department wants to temporarily withdraw and then renegotiate an agreement
  • Synchronizing clock sources for Agilent Pattern Generator 70841B
    The purpose of this application note is to provide design guidance, test techniques, performance data and suggested layout. recommendations for a 622 MBd ATM/SONET/SDH physical layer interface reference circuit. This standards-compliant reference design provides a convenient, interchangeable
  • EETimes.com | Electronics Industry News for EEs & Engineering Managers
    Cadence looks to overhaul chip design flow A bold technology initiative that aims to reshape the way designers tackle logical and physical IC design is under way at Cadence Design Systems Inc. By focusing first on chip-level assembly, the internally labeled Nano Project that's brewing at Cadence

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