TABLE OF CONTENTS We will now turn to a four-transistor cell which is not strict-TL in form (the loop is broken, making it a TN form) but which is very closely related and has so many uses, both by itself and embedded into TL circuits, that it is deserving mention in this context.
The generic cell is shown in Figure 2.41. In some way, a current Ia is established in Ql and Q2 and Ib in Q3 and Q4. The voltage in the open port is
V = V BE4 + V BE1 - V BE3 - V BE2
and since, in the ideal case where there are no base currents,
V BE1 = V BE2 and V BE3 = V BE4
it follows that V is always zero, whatever values Ia and Ib may have! A real circuit can come quite close; it's easy to show that
| (2.41) |  |
For a ratio Ia/Ib=10 and ?=100, V would be about 2.5mV; Figure 2.42 shows the form of V with Ia fixed and Ib swept from 100 ?A at 10mA. Conversely, V could be viewed as the voltage required to establish a 10:1 current ratio in the two pairs of transistors. Note that this is much lower than the "60mV per decade" associated with a simple pair of junctions. If we let Ia=Ib=I, the input resistance is found to be
| (2.42) |  |
We should always be cautious when it appears we're getting something for...
