The Foundations of Digital Signal Processing: Theory, Algorithms and Hardware Design

Chapter 15: The Design and Programming of Real-time DSP Systems Part 2: Hardware and Algorithms

15.1 Introduction

Now that we have looked at some of the internal design features that allow the DSP56309 [1] to perform arithmetic operations so quickly and efficiently, we can move on to consider a simple but very useful and flexible real-time DSP system incorporating the DSP56309 as the core processor. Although quite straightforward in concept, the design is suitable for advanced stereophonic signal processing of audio bandwidth signals, and is shown in schematic form in Figure 15.1. This design utilises a dual channel audio codec, 256 kbytes of external flash memory for holding data or boot-up code and facilities for communicating directly with the serial interface of a PC. To keep the design as straightforward as possible, we have omitted external static random access memory (SRAM). This is not a problem here because the device s internal memory area is large enough to accommodate programs of considerable size and complexity. Because the system has both flash and a PC interface, it may operate either as a stand-alone processing environment or as a slave unit connected to a computer. As Figure 15.1 also indicates, a number of the control signals are tied to the power rail or ground by 15 k ? resistors. This is because of the operating mode that has been selected for this system; these signals will be discussed as we encounter them, later in the text.


Figure 15.1: Principal components of a real-time DSP system using the DSP56309, incorporating a serial PC interface, 256 kbytes of...

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