Fault simulation constitutes an indispensable tool in ensuring the correctness and quality of manufactured digital designs. Traditional uniprocessor-based algorithms for fault simulation have been observed to be agonizingly slow for today's large and complex digital designs. More recently, a few researchers introduced an approach, as evident in the literature, wherein the fault set is partitioned and the digital design fault simulated for each fault subset on separate processors of a parallel processor system. The approach is limited in that it continues to use the traditional uniprocessor-based algorithm and the performance results are not encouraging. This section introduces a distributed algorithm that is capable of fault simulating both combinational and asynchronous sequential digital designs on parallel processors. An underlying assumption of the algorithm is that the digital design, under fault simulation, is partitioned by the user. In this approach, referred to as NODIFS, every component in the circuit is modeled as an asynchronous, concurrent entity that is fault simulated as soon as appropriate signal transitions and fault lists are asserted at its input ports. The circuit partitioning is such that components of every partition are allocated to a unique processor of the parallel processor system. Consequently, a number of components may be concurrently fault simulated on multiple processors in NODIFS, implying significant increase in throughput. This approach promises (1) very high throughput because of its ability, in principle, to utilize the maximal inherent parallelism...
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