This section presents a new approach, P 2 EDAS, that is capable of asynchronous and concurrent simulation of VHDL models on parallel processors, including the detection and preemption of inconsistent events. This section is organized as follows. Section 3.1.1 introduces the concept of simulation of digital computer systems and the key challenges to ensure accuracy in today's complex systems. Section 3.1.2 details the P 2 EDAS algorithm, and Section 3.1.3 presents an example to illustrate the approach. Section 3.1.4 reports on the implementation of P 2 EDAS on both a multithreaded shared memory multiprocessor and a network of workstations configured as a loosely coupled parallel processor and presents performance data for representative designs. The mathematical proof of correctness of P 2 EDAS is presented, with the proofs of other algorithms, in Chapter 5.
The principal objective [76] of the DoD VHDL [77] hardware description language has been to allow digital hardware designs to be described, simulated, and validated accurately and efficiently in the computer, prior to building a prototype. In addition, an important objective of VHDL [76] has been to allow the execution of VHDL processes in parallel on multicomputers and multiprocessors. To date, the execution of VHDL models continues to be limited to uniprocessors and is excruciatingly slow. The literature relative to deadlock-free, null-message-free, and conservative algorithms...
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