Overview

Over the past 20 years, the channel length of MOS transistors has been halved at intervals of approximately three or four years. The continuous shrinking of the size of MOS transistors has led to increasing performance (clock speed) in electronic systems (e.g., computers, mobile phones) and increasing packing density in Si chips. As a result, increasingly sophisticated and powerful electronic products have appeared at prices similar to earlier generations of the product. The question that arises is how long this trend can continue.

A number of factors are posing a threat to this evolution of CMOS scaling technology. The reasons are manifold. First, the channel length of the MOS transistor is defined using optical lithography, which is limited by the wavelength of light. It therefore becomes increasingly difficult to design new generations of optical lithography tools. The current thinking is that optical lithography can reach channel lengths of around 0.15 ?m, but it is not clear whether it can meet the challenge of smaller geometries. Instead of defining the channel length of a lateral MOS transistor using lithography, an effort is being made to define the channel length of a vertical MOS transistor using epitaxy. Extremely thin layers can be produced using epitaxy which would allow MOS transistors to be produced with channel lengths below 0.025 ?m.

Secondly, short channel effects such as drain induced barrier lowering (DIBL) and punch-through problems become more difficult to manage. It is becoming increasingly difficult to obtain shallow enough source and...