6.10 CMOS Class-E Power Amplifiers

Recent progress in CMOS technology has shown their promising future for RF power application. Much progress has been achieved at the research level, and the obvious possibility to minimize the cost and size of the integrated circuits for RF handset transmitters, especially power-amplifier MMICs, makes CMOS technology very feasible and brings considerable economic benefits. However, realizing high-efficiency operation of power amplifiers is limited by some technology issues, such as the high value of the device saturation resistance, low value of the breakdown voltage, and lossy silicon substrate. Therefore, it is vital to apply high-efficiency technique in the design of the CMOS power amplifiers.

For example, a 900-MHz cascode power amplifier based on a 0.25-/xm CMOS technology with active die area of 2 x 2 mm ² can provide an output power of 0.9 W and a power-added efficiency of 41% using a Class-E load network with shunt capacitance and finite dc-feed inductance, the circuit schematic of which is shown in Fig. 6.34 [40]. Minimizing the value of the dc-feed inductance is necessary to minimize the die size, resulting also in higher values of the load resistance and shunt capacitance required for a nominal Class E with finite dc-feed inductance. For the same value of saturation resistance, this contributes to lower power loss on the active device and can absorb a larger value of the device output capacitance. Cascode configuration and thick-oxide transistors are used to eliminate the effects of oxide breakdown voltage and hot-carrier...