6.6 Large Size

With the advent of Generation 5, 6, and 7 production lines for a-Si TFT LCDs, it has become possible to build very large displays with a size approaching that of the largest plasma displays. Before LCDs larger than 40 in. or with resolution higher than SXGA became possible, several technical hurdles had to be overcome. One is, of course, manufacturing yield, discussed in Chapter 3, Sec. 3.9. Another is the line resistance of the select and data buslines. When the signal propagation delays on the buslines becomes a significant fraction of the line select time, LCD performance can deteriorate.

This is the case also for 20- to 25-in. displays with very high resolution in the UXGA to QUXGA range, developed for graphics and medical imaging applications. They have a very short line select time, as shown earlier in Table 5.3.

Long buslines or short select line times both require the use of low-resistance gate lines to minimize the RC propagation delays. Figure 6.37 shows how the select pulse is distorted along the select line of a large or high-resolution display. The load on each pixel can be represented by a resistance R/N and capacitance C/N, where N is the number of pixels on a row. A distributed network of these capacitors and resistors represents the entire row. Both the rise time and the decay time of the gate pulse are increased at the end of the row line.

Figure 6.37: Equivalent circuit for gate busline with resistance...