TABLE OF CONTENTS Many design techniques have been developed to reduce power and by the judicious application of these techniques, systems are tuned for the best power/performance trade-offs.
A common engineering philosophy when designing a System-on-a-Chip (SoC) is to insure that they perform under "worst-case" conditions. Worst case in semiconductor manufacturing applies to very high temperatures and variations in the manufacturing process; transistor performance varies in a predefined range of parameters. Thus, some SoCs from the same wafer lot are capable of supporting higher operating frequencies (best case fast process) or lower frequencies at the bottom of the predefined performance window (worst case slow process) at the given voltage (Figure 3.1).
Dynamic process temperature compensation (DPTC) mechanism measures the frequency of a reference circuit that is dependent on the process speed and temperature. This reference circuit captures the product's speed dependency on the process technology and existing operating temperature and lowers the voltage to the minimum level needed to support the existing required operating frequency (Figure 3.2).
A mobile device containing a fast-process SoC operating in a moderate climate condition can be expected to work at the worst-case calculated voltage to support the required frequency. This is less than an optimum energy savings.
The DPTC concept allows the supply voltage to be adjusted to match the process corner and SoC temperature. If the process corner is "best case" a...
