TABLE OF CONTENTS Historically packaging plays two roles. First, it provides I/O connections to and from discrete integrated circuits; second, it interconnects both active and passive components on system-level boards. Integrated circuits have begun to integrate not only more transistors, but also active and passive components on an individual chip, leading to as SoC. However, the disparate process technologies that are required to manufacture digital and analog integrated circuits limit the ability to develop, manufacture, and test highly integrated systems in an economic fashion.
Therefore, the SoCs approach presents fundamental, engineering, and investment limits, as well as computing and communication limits for wireless and wired systems over the long run. In addition the packaging that is used to provide I/O connections from the chip to the rest of the system is typically bulky and costly, limiting both the performance and the reliability of the IC it packages. Systems packaging, involving the interconnection of components on a system-level board, is similarly bulky and costly with poor electrical and mechanical performance.
This led to packaging approaches like multi-chip modules (MCM), system-in-package (SiP), package-on-package (PoP), and future 3D packaging technologies like redistributed chip packaging (RCP) and systems-on-package (SoP). Figure 8.15 shows the evolution of systems packaging.
RCP eliminates the substrate and the need for intermediate interconnects typically found with IC packaging solutions such as flip chip ball grid array (BGA) and wirebond ball grid array. These technologies...
