This API provides your applications with driver-level access to the highspeed serial (HSS) and high-level data link control (HDLC) co-processors available on NPE A. This API and its supporting NPE-based hardware acceleration enable the IXP4XX network processors to support packetized or channelized TDM data communications.

The channelized service provides your code with the raw serial data streams retrieved from the HSS port, while the packetized service provides packet payload data that the processor has processed according to the HDLC protocol.

The HSS co-processor enables the IXP42X network processors to communicate externally, in a serial-bit fashion, using TDM data. T1, E1, and MVIP bit-stream protocols are supported. The HSS co-processor can also interface with xDSL framers.

The HSS co-processor communicates with an external device using three signals per direction: a frame pulse, clock, and data bit. The data stream consists of frames the number of frames per second depending on the protocol. Each frame is composed of time slots. Each time slot consists of 8 bits (1 byte) that contain the data and an indicator of the time slot's location within the frame.

The maximum frame size is 1,024 bits and the maximum frame pulse offset is 1,023 bits. The line clock speed can be set to one of the following values to support various E1, T1, or aggregated serial (MVIP) specifications:

• 512 kilohertz

• 1.536 megahertz

• 1.544 megahertz

• 2.048 megahertz

• 4.096 megahertz

• 8.192 megahertz

The frame size and frame offsets are all programmable depending on the protocol. Other programmable options include...