TABLE OF CONTENTS PLLs designed for frequency synthesis employ a variable-frequency divider, which provides programmability and enables the use of reference crystal oscillators. The two main issues related to the design of the frequency divider are the high input frequency and the programmability of the division factor. As will be made clearer in this chapter, wide variations of the division factor and high input frequency are opposing requests. To some extent, higher operation frequency can be traded against power consumption. However, as we will show, smart architectural choices can allow for much higher frequency of operation with the same power consumption and technology process. The input sensitivity that is the minimum required amplitude of the input signal is also of great concern in high-speed dividers.
Digital dividers are based on either flip-flops or latches, using either static or dynamic logics. Analogue implementations of divide-by-two circuits relying on injection locking or parametric amplification also exist. Depending on their implementation, dividers have different noise generation mechanisms. However, a lower phase noise generally demands higher power consumption.
This chapter discusses typical techniques for realizing programmable dividers, with particular emphasis on such topologies as allow for maximum speed in a given semiconductor process. The circuit implementations of the building blocks will be reviewed. Finally, methods for predicting the noise of digital frequency dividers will be examined.
Digital frequency dividers by M are modulo- M counters. The most significant bit (MSB) of a modulo- M counter provides a signal...
