TABLE OF CONTENTS The programming model of the IXP2XXX processor differs from traditional programming models, such as those used in a Windows- or Linux-based environment. In traditional programming models, operating systems abstract the concepts of threads and memory hierarchies and thus virtualize most, if not all, of the hardware. However, when programming the IXP2XXX processor, you must be aware of the hardware, including threads and different memory types, to produce optimized code and let the hardware do what it was designed to do.
Understanding the IXP2XXX programming environment goes beyond just learning another set of software programming interfaces. Understanding the IXP2XXX programming environment means understanding the processor architecture. But consider the upside. By taking advantage of the IXP2XXX hardware, you can offload work to it. One less thing to write and debug is always a win.
This chapter describes the components of the processor s architecture relevant to programmers. Typically, such descriptions provide good reference material, but can be difficult to remember. So, to put the pieces of the processor architecture into perspective, the description is followed by a practical, and hopefully memorable, explanation of a day in the life of a packet in the IXP2XXX hardware.
As shown in Figure 2.1, the IXP2850 consists of 17 programmable processors: one Intel XScale core and 16 second-generation microengines [1] all on the same die. The Intel XScale core is an Advanced Reduced Instruction Set Computer (RISC) machine that is compliant with ARM Architecture V5STE, general-purpose processor. The microengines are...
