Glossary

Advanced Encryption Standard (AES): is a cryptographic algorithm initiated by the National Institute of Standards and Technology (NIST) to replace DES and its variations. The IXP2850 processor implements this algorithm in the IXP2850 crypto unit.
Arbiter: is also referred to as the thread arbiter. On the IXP2XXX microengines, the arbiter selects the next thread to execute in a round-robin fashion.
Asynchronous Insert/Synchronous Remove (AISR): is a data structure that serves as a mechanism to ensure packet ordering in the unordered thread execution programming model.
Atomic Memory Operation: is a multi-access, Read-Modify-Write (RMW) memory operation in which no other memory accesses are interleaved between the separate memory accesses of the RMW. Atomic memory operations are important when updating critical data so software mechanisms aren t needed to lock the data during updates.
Cbus: is a CSIX flow control bus used to connect an egress IXP2XXX network processor that receives flow control messages to an ingress IXP2XXX network processor that is responsible for scheduling the data to be transmitted.
Cframe: is a CSIX frame. The three categories of Cframes are: data, control, and flow control.
Common Switch Interface (CSIX): defines an interface between a traffic manager and a switch fabric for data communications applications. The Network Processor Forum (NPF), controls the CSIX-L1 specification. The traffic manager in CSIX refers to any device using the CSIX-L1 interface, including a network processor, such as the IXP2XXX processor.
Content Addressable Memory (CAM): is a memory technology that allows the parallel search of the memory s...

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IXP2400/2800 Programming: The Complete Microengine Coding Guide

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IXP2400/2800 Programming: The Complete Microengine Coding Guide

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