TABLE OF CONTENTS In Chapters 2 and 3, you were introduced to the architecture resources of the Itanium processor such as the application register set, data types, memory, and the instruction set as well as high-level language and assembly language programming. This chapter examines parallel processing and the techniques, such as upward and downward code motion, that enable the compiler to increase parallel execution of instructions and efficiently use the Itanium processor s parallel execution resources.
Instruction level parallelism (ILP) is the key to the Itanium processor s ability to deliver a sustained higher level of performance. ILP enables many things to be done at once that is, parallel processing. In fact, the Itanium processor can issue up to six instructions at a time. The traditional problem is that there is never enough work to always keep the machine fully busy. Any time that the processor is ready and is not given six more things to do, processing resources go unused. For this reason, the Itanium processor incorporates many advanced architectural capabilities that are targeted at increasing parallel execution.
As long as instructions in a program are independent, they can be executed in parallel. For an instruction to be independent, its result cannot be affected by another instruction. A set of contiguous instructions that are independent is called an instruction group.
The Itanium processor requires the compiler to analyze the sequential instruction stream of the program to identify those instructions that are dependent, and to rearrange the sequence by grouping together those that are...
