TABLE OF CONTENTS When a particular program has been extensively optimized and single computer performance remains inadequate, parallel execution may be in order. Parallel computation is a rather significant leap from most of the coding conventions presented in Part II, and only a brief introduction is presented in this Chapter. The reader interested in (or requiring) parallel performance is encouraged to read the listed and similar references for specific information. Finally, in keeping the style of earlier chapters, only desktop computers are considered here for simplicity.
There are various techniques useful for parallel computation. Each has merits for particular tasks. Several approaches are briefly outlined in this section, and more detail is presented in Sections 12.2 and 12.3. There may be some overlap in these techniques, and others may exist.
As discussed in Sections 2.5 and 2.7, many modern PC CPU's are designed with multiple execution units. These are implemented at the hardware level, with the CPU circuitry scheduling the decoded microinstructions for optimal performance. Performance can be further enhanced by the order in which CISC level instructions (as compiled from a high-level language) are presented to the CPU for decoding. The reader can imagine cases in which the order of source code lines do not matter logically for proper program execution; a point often overlooked, however, is that these 'equivalent' codes may not execute in the same number of CPU cycles due to scheduling within the CPU.
As an example,...
