SERDES macrocell circuits receive fast serial signals on the order of mbit/s or higher and de-serialize them into slower, parallel signs. They are used in high-speed communications and include a DC-balanced coding scheme such as 8B/10B encoding. SERDES is an abbreviation for serializer/de-serializer. They include serializers that function as serial-to-parallel converters and deserializers or receivers that convert parallel data into serial form. Most SERDES macrocells are low-power, high-performance devices. Using a SERDES chip can reduce the number of necessary wires or pins by transmitting parallel data between two points over a serial stream. Some SERDES circuits can be programmed like any other programmable logic device (PLD).
A SERDES circuit consists of integrated serializers and deserializers that can be used to convert parallel data into serial form, or serial data into parallel form. Typically, a SERDES circuit includes SERDES memory. When data bits are transmitted, a start bit at the beginning and a stop bit at the end are appended so that the receiver can determine where the packet starts and ends. Advanced on-chip diagnostic intelligence helps to test and monitor high-speed serial links for the determination of the bit error rate. As a rule, the speed of a SERDES chip is a function of the device with which it is used. In some cases, the operating speed can exceed 10 Gbps; however, a SERDES circuit is usually used with devices that are capable of handling 3.125 to 3.75 Gbits/s. Other SERDES macrocell circuits may carry additional specifications.
SERDES circuits are designed and manufactured to meet most industry specifications. They are often used in applications such as wireless network routers, fiber optic communication systems, and gigabit Ethernet systems. Some SERDES circuits are used in line card applications. SERDES chips should adhere to standards from organizations such as the Institute of Electrical and Electronics Engineers (IEEE).