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Designers face many decisions when implementing a Finite Impulse Response (FIR) filter within an FPGA design. Which parameters are important? What is the best way to approach the design? How should this design be implemented within an FPGA? But the challenge is not as daunting as it sounds. Because FIR filters are among the most common functions implemented within FPGAs, plenty of low-cost IP cores and tools are available to facilitate the design implementation.

Important FIR filter parameters

In their simplest form, FIR filters generate their outputs y(n) by averaging the last N inputs of sample data, x(n). Each sample stored is called a tap. Most designs are a little more complicated than this; to provide optimal filter characteristics, it is common to multiply each tap by a coefficient or weighting value, h(i). Figure 1 illustrates a typical FIR filter structure (fully parallel).

The key parameters for a FIR filter are the passband, stopband, stopband attenuation, and passband ripple. Figure 2 shows these parameters for a low-pass filter. For some applications, stopband ripple also may be important and specified. However, stopband attenuation is adequate for most applications. An input sampling rate and desired output sampling rate will be included, along with input and output data resolutions.

Ultimately, the application defines many of the design specifications, though some guidelines can help designers narrow down the possibilities and evaluate design trade-offs. Generally, the closer the passband is to the stopband, the more challenging the design will be. Similarly, specifying very low ripple in the passband or very high stopband attenuation greatly increases the design’s complexity.